cx20493-35/app Conexant Systems, Inc., cx20493-35/app Datasheet - Page 86

• Manufacturer Part Number: cx20493-35/app
• Description: With Cx20493 Smartdaa?
• Manufacturer: Conexant Systems, Inc.

5-8
CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
This bit, when set, indicates that the TX Buffer is empty and the modem can accept a
In the FIFO mode, this bit is set when the TX FIFO is empty; it is cleared when at least
This bit is set to a 1 whenever the received data input is a space (logic 0) for longer
This bit indicates that the received character did not have a valid stop bit. The FE bit is
In the FIFO mode, the error indication is associated with the particular character in the
This bit indicates that the received data character in the RX Buffer does not have the
In the FIFO mode, the error indication is associated with the particular character in the
This bit is set to a 1 whenever received data is loaded into the RX Buffer before the
In the FIFO mode, if data continues to fill beyond the trigger level, an overrun
This bit is set to a 1 whenever a complete incoming character has been received and
In the FIFO mode, the DR bit is set when the number of received data bytes in the RX
new character for transmission. In addition, this bit causes the modem to issue an
interrupt to the host when the Transmit Holding Register Empty Interrupt Enable bit
(IIR1) is set to 1. The THRE bit is set to a 1 when a character is transferred from the
TX Buffer. The bit is reset to 0 when a byte is written into the TX Buffer by the host.
one byte is in the TX FIFO.
than two full word lengths plus 3 bits. The BI bit is reset when the host reads the LSR.
set to a 1 whenever the stop bit following the last data bit or parity bit is detected as a
logic o (space). The FE bit is reset to a 0 when the host reads the LSR.
FIFO it applies to; the FE bit is set to a 1 when this character is loaded into the RX
Buffer.
correct even or odd parity, as selected by the Even Parity Select bit (LCR4) and the
Stick Parity bit (LCR5). The PE bit is reset to a 0 when the host reads the LSR.
it applies to; the PE bit is set to a 1 when this character is loaded into the RX Buffer.
host has read the previous data from the RX Buffer. The OE bit is reset to a 0 when the
host reads the LSR.
condition will occur only if the RX FIFO is full and the next character has been
completely received.
has been transferred into the RX Buffer. The DR bit is reset to a 0 when the host reads
the RX Buffer.
FIFO equals or exceeds the trigger level specified in FCR0-FCR1.
Transmitter Holding Register Empty (THRE) [TX Buffer Empty].
Break Interrupt (BI).
Framing Error (FE).
Parity Error (PE).
Overrun Error (OE).
Receiver Data Ready (DR).
Conexant
102247B