cx20493-35/app Conexant Systems, Inc., cx20493-35/app Datasheet - Page 40

• Manufacturer Part Number: cx20493-35/app
• Description: With Cx20493 Smartdaa?
• Manufacturer: Conexant Systems, Inc.

Table 3-2. CX81801 Modem Pin Signal Definitions for Parallel Interface (PARIF = High)
3-8
XTLI,
XTLO
CLKIN
CLKOUT
DV1TP
PARIF
LINE_SEL (PE7)
STPMODE# (PD3)
NMI#
RESET#
VGG
VDD
VDD_CORE
GND
LPO
NOXYCK
PLLVDD
PLLGND
NVMCLK (PA7)
NVMDATA (PE3)
CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet
Label
114,
115
113
61
111
5
23
9
117
34
60
2, 15, 40, 58,
78, 100, 108,
116, 124
20, 53, 85
10, 25, 30, 44,
48, 68, 90, 95,
103, 112, 120,
128
57
47
82
83
33
18
Pin
I,
O
I
O
I
I
I
I
I
I
P
P
P
G
I
I
P
G
O
I/O
I/O
Serial EEPROM (NVRAM) Interface
Ix,
Ox
It
It/Ot2
Itpu
Itpu
It/Ot8
Ith/Ot2
Ithpu
It
PWRG
PWR
PWR
GND
I/O
Itpu
PWR
GND
It/Ot2
It/Ot2
I/O Type
Conexant
System
Crystal In and Crystal Out. If an external 28.224 MHz crystal
circuit is used instead of an external clock circuit, connect XTLI
and XTLO to the external crystal circuit and connect CLKIN to
digital ground (GND).
Clock In. If an external 28.224 MHz clock circuit is used instead of
an external crystal circuit, connect CLKIN to the clock output and
leave XTLI and XTLO open.
Clock Out. 28.224 MHz output clock. Leave open.
Clock Input Select. This input is used to choose the clock input.
Connect to +3.3V or leave open to select XTLI as the clock input.
Connect to GND to select CLKIN as the clock input.
Parallel/Serial Interface Select. PARIF input high (open) selects
parallel host interface operation (see this table); PARIF low (GND)
selects serial DTE interface operation (see Table 3-4).
Line Interface Select. Selects telephone line interface. Connect to
+3.3V though 47 KΩ.
Stop Mode. Not used. Leave open.
Non-Maskable Interrupt. Not used. Connect to +3.3V.
Reset. The active low RESET# input resets the Smart Modem
logic, and restores the saved configuration from serial EEPROM or
returns the modem to the factory default values if NVRAM is not
present.
RESET# low holds the modem in the reset state; RESET# going
high releases the modem from the reset state. After application of
VDD, RESET# must be held low for at least 15 ms after the VDD
power reaches operating range. The modem device set is ready to
use 25 ms after the low-to-high transition of RESET#.
For parallel Interface, connect RESET# input to the host bus
RESET line through an inverter.
I/O Signaling Voltage Source. Connect to +3.3V for +3.3V inputs,
or to +5V for +5V inputs.
Digital Supply Voltage. Connect to VCC (+3.3V, filtered).
Core Voltage. Internal core voltage.
Digital Ground. Connect to digital ground (GND).
Low Power Oscillator. Connect to +3.3V through 240 KΩ.
Disable XCLK Output. When low, disables XCLK output (reduces
internal power consumption). When high, enables XCLK output.
Connect to GND.
PLL Circuit Digital Supply Voltage. Connect to +3.3V and to
GND through 0.1 µF.
PLL Circuit Digital Ground. Connect to GND.
NVRAM Clock. NVMCLK output high enables the EEPROM.
Connect to EEPROM SCL pin.
NVRAM Data. The NVMDATA pin supplies a serial data interface
to the EEPROM. Connect to EEPROM SDA pin and to +3.3V
through 10 KΩ.
Signal Name/Description
102247B