cxd3220r Sony Electronics, cxd3220r Datasheet - Page 61

• Manufacturer Part Number: cxd3220r
• Description: Ieee1394 Link/transaction Layer Controller Lsi For Sbp-2
• Manufacturer: Sony Electronics

Consider a case in which two different nodes confirm that the packet sent is addressed to them (one is correct,
one is wrong), and both nodes issue an Acknowledge request before CRC check. The Phy of both nodes try to
capture the bus immediately after packet receive is completed. In this state, a momentary collision occurs on
the local bus at some point between the two Phy that sent back Acknowledge. This can be detected by all of
the Phy connected to the bus. This collision is not interpreted as bus reset, but as high impedance state. After
CRC check is completed, the wrong node will withdraw its request and the high impedance state is
discontinued. The expected Acknowledge is lost as a side effect of this, but is processed by the host protocol.
8-2-2-2. Read/Write Request
When the CXD3220R requests reading of a specific register's contents, Phy transmits the register contents to
the CXD3220R by Status Transfer. Even if packets are received while Phy is sending status information to the
CXD3220R, Phy continues processing until the register contents are transferred.
For a Write request, Phy loads the data fields into the appropriate register as soon as transmission is
completed. The CXD3220R can read/write at any time.
8-2-3. Status
Status transmission is started by Phy when it has some data to transmit to the CXD3220R. Phy begins
transmission by simultaneously setting CTL [0:1] to "01b" and the first 2 bits of Status information to D [0: 1].
Phy maintains CTL = Status during status transmission.
Phy may finish Status transmission early by setting the CTL value to some other value. This happens if a
packet arrives before Status transmit is completed.
There must be at least one idle cycle in a continuous Status transmission.
Phy normally sends the first four bits of Status to the CXD3220R. These bits are the Status Flags required for
the CXD3220R state machine. When transmission of a request containing a Read Request is completed, or
when Phy has information to send to the CXD3220R or the Transaction Layer, Phy sends the first Status
packet to the CXD3220R.
The only state in which Phy sends register contents automatically to the CXD3220R is that after completion of
Self-Identification, and Physical_ID register contents containing a new node address are transmitted. The
transmit timing and bit definitions are illustrated below.
PHY Ctl [0:1]
PHY D [0:1]
00
00
S [0, 1]
01
S [2, 3]
01
– 61 –
S [14, 15]
01
00
00
00
00
CXD3220R