cxd3220r Sony Electronics, cxd3220r Datasheet - Page 16
cxd3220r
Manufacturer Part Number
cxd3220r
Description
Ieee1394 Link/transaction Layer Controller Lsi For Sbp-2
Manufacturer
Sony Electronics
Datasheet
1.CXD3220R.pdf
(65 pages)
- Current page: 16 of 65
- Download datasheet (414Kb)
3) Control Register
These registers perform settings for the CXD3220R basic operations.
The register address is 08h; they are for read/write, and the initial value is C600_2A01h.
29 to 27
Bit
31
30
26
25
21
20
13
12
11
10
9
3
0
idVal
RxSld
BsyCtrl
TxEn
RxEn
RstTx
RstRx
AIDT16
AckCtl
CyMasEn
CySrc
CyTEn
StrSid
LPS
Name
Receives packet from the address set in the Node Address register and
packet at bus number "3FFh" node number "3Fh" when "1". Receives packet
at bus number "3FFh" node number "3Fh" only when "0".
Validates reception of Self ID packet when "1". Non-valid when "0".
(Fixed at "1" in the CXD3220R)
Controls Busy status of input packet
000 = Returns Busy according to normal Busy/retry protocol when necessary.
(Fixed at "000" in the CXD3220R)
Transmitter does not transmit Arbitration and packet when "0".
Receiver does not receive packet when "0".
Sync resets transmitter when "1".
This bit is cleared automatically. (Do not use for normal operation.)
Sync resets receiver when "1".
This bit is cleared automatically. (Do not use for normal operation.)
Selects SD bus width. 8 bits when "0" and 16 bits when "1".
Controls the Ack code that is sent back when a packet is received for which
Tcode = 0, 1 (write request quadlet/block).
The Cycle Master function operates if the CXD3220R becomes Root when "1".
Incrementation of the cycle number and reset of Cycle Offset are performed
with Cycle In when "1". Incrementation is performed with Cycle Offset when
"0". (This is always set to "0" internally for this link.)
Validates Cycle Offset increment when "1".
(This is always set to "1" internally for this link.)
Takes received Self ID packet in at the ARF when "1".
Does not take received Self ID packet in to the ARF when "0".
The LPS pin is high when "1".
The LPS pin is low when "0".
0: Ack code = 1 (complete), 1: Ack code = 2 (pending)
– 16 –
Function
CXD3220R
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