cxd3220r Sony Electronics, cxd3220r Datasheet - Page 17

• Manufacturer Part Number: cxd3220r
• Description: Ieee1394 Link/transaction Layer Controller Lsi For Sbp-2
• Manufacturer: Sony Electronics

4) Interrupt and Interrupt-Mask Registers
These registers combine the Interrupt register, which informs the CPU I/F of changes in the CXD3220R status,
and the Interrupt-Mask register, which masks the Interrupt register.
The address of the Interrupt register is 0Ch, and when the regRW bit is "0", bits other than Int bit and ADPErr
bit are cleared by writing "1". When the regRW bit is "1" all bits are for read/write.
The address of the Interrupt-Mask register is 10h and it is for read/write. When "1" is written to the
corresponding bit, the interrupt becomes valid; when "0" is written, it becomes invalid.
The initial value for both registers is 0000_0000h. The Interrupt OR corresponding to the bit where "1" is
written in the Interrupt-Mask register becomes the INT bit, resulting in the XINT output signal.
And the XINT output signal becomes valid when "1" is written to the Interrupt-Mask register INT bit; when "0" is
written, invalid.
Bit
31
30
29
28
27
26
25
24
23
22
20
19
17
16
15
11
10
9
8
7
6
Int
PhyInt
PhyRegRx
BusRst
FairGap
TxRdy
RxDta
CmdRst
EndSlf
RcvAck
ITStk
ATStk
SntRj
HdrErr
TCErr
CySec
CycSt
CycDne
CycPnd
CycLst
CyAbFail
Name
All interrupt OR results and their interrupt mask bits.
Phy Interrupt was received from Phy chip.
Data was received from Phy to Phy register.
Bus Reset was received from Phy.
Fair Gap received from Phy.
Transmitter is able to transmit. "0" when a packet is transmitted; "1" when an
Ack code is fixed.
Receiver has received a correct packet. A packet is not loaded in the ARF
when the Self-ID packet is received if the Control register Strsid is set to "0"
and when the Response packet is received at the ADP circuit for ADP
operation. However, RxDta Interrupt is set.
Receiver has received a packet addressed to CSR RESET_START register.
Indicates that Self ID phase has completed.
Ack code was received.
Transmitter detected wrong data in Isochronous FIFO during Isochronous
transmit. (Always set to "0" in this IC)
Transmitter detected wrong data in Asynchronous FIFO during Asynchronous
transmit.
Receiver transmitted Busy Ack for a packet transmitted to this node because
received FIFO is full.
Receiver detected Header CRC error in the packet transmitted to this note.
Transmitter detected wrong tCode data in transmitted FIFO.
Cycle Timer register Cycle Number upper 7 bits were incremented.
(This is generated almost every second when Cycle Timer is valid.)
Transmitter/Receiver transmitted/received Cycle Start packet.
After transmit or receive of Cycle Start packet, Fair Gap was detected on the
bus. This means that the Isochronous cycle is complete.
Cycle Timer register Cycle Offset is "0". Stays as is until Isochronous cycle is
complete.
When not Cycle Master, Cycle Timer completed two cycles without receiving
Cycle Start packet.
Failure of Cycle Start packet transmission Arbitration.
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Function
CXD3220R