lxt971a Intel Corporation, lxt971a Datasheet - Page 8

• Manufacturer Part Number: lxt971a
• Description: 3.3v Dual-speed Fast Ethernet Phy Transceiver
• Manufacturer: Intel Corporation

LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver
Revision History
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Globally replaced “pseudo-PECL” with Low-Voltage PECL”, except when identified with 5 V.
Front Page: Changed “pseudo-ECL (PECL)” to “Low Voltage PECL (LVPECL).
Added “JTAG Boundary Scan” to Product Features on front page.
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Added note under
function pins be tied to the inactive states and all outputs be left floating, if unused.”
Modified SD/TP description in
Added Table note 2.
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Replaced second paragraph under
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Changed “Far-End Fault” title to
Modified first sentence under this heading.
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Table 8 “LXT971A Pin Types and
Section 3.2.2.1, “Increased MII Drive
Figure 26 “Typical LXT971A-to-5 V Fiber Transceiver Interface
Figure 27 “ON Semiconductor Triple PECL-to-LVPECL
Table 23 “I/O Characteristics – SD/TP
Table 28 “LXT971A Thermal
Table 57 “Digital Config Register (Address
Section 8.0, “Product Ordering
Figure 2 “LXT971A 64-Ball PBGA Assignments”
Figure 3 “LXT971A 64-Pin LQFP Assignments”
Table 1 “LQFP Numeric Pin List”
Table 4 “LXT971A Miscellaneous Signal
Table 5 “LXT971A Power Supply Signal
Figure 8 “Hardware Configuration
Table 13 “Supported JTAG
Table 14 “Device ID
Table 17 “Absolute Maximum
Table 18 “Operating
Table 20 “Digital I/O Characteristics - MII
Table 22 “I/O Characteristics - LED/CFG
Table 33 “10BASE-T Receive Timing Parameters”
Table 42 “Register Bit
Table 58 “Transmit Control Register (Address
Figure 25 “Typical LXT971A-to-3.3 V Fiber Transceiver Interface
Section 4.3, “The Fiber
Section 2.0, “Signal
Section 3.7.3.4, “Fiber PMD
Revision Date: August 6, 2002
Register”.
Conditions”: Added Typ values to Vcc current.
Table 3 “LXT971A Network Interface Signal
Map”. (Added Table 26 information).
‘100BASE-FX Far-End
Section 3.2.1.2, “Fiber
Characteristics”.
Revision 002
Instructions”.
Section 3.6.7.2, “Test
Interface”.
Information”.
Descriptions”: “Intel recommends that all inputs and multi-
Ratings”.
Modes”.
(replaced TEST1 and TEST0 with GND).
Settings”.
Description
Strength”.
Pin”.
Sublayer”.
Descriptions”.
Descriptions”.
26)”.
Pins”.
Pins”.
30)”.
Fault”.
(replaced TEST1 and TEST0 with GND).
(replaced TEST1 and TEST0 with GND).
Interface”.
Loopback”.
Translator”.
Circuitry”.
Descriptions”.
Circuitry”.
Rev. Date: August 7, 2002
Document #: 249414
Revision #: 002
Datasheet