lxt971a Intel Corporation, lxt971a Datasheet - Page 44

• Manufacturer Part Number: lxt971a
• Description: 3.3v Dual-speed Fast Ethernet Phy Transceiver
• Manufacturer: Intel Corporation

LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
3.8.4
3.8.4.1
3.8.5
3.8.6
3.8.7
3.9
3.9.1
44
10BASE-T Link Integrity Test
In 10BASE-T mode, the LXT971A always transmits link pulses. When the Link Integrity Test
function is enabled (the normal configuration), it monitors the connection for link pulses. Once link
pulses are detected, data transmission is enabled and remains enabled as long as either the link
pulses or data transmission continue. If the link pulses stop, the data transmission is disabled.
If the Link Integrity Test function is disabled, the LXT971A transmits to the connection regardless
of detected link pulses. The Link Integrity Test function can be disabled by setting Register bit
16.14 = 1.
Link Failure
Link failure occurs if the Link Integrity Test is enabled and link pulses or packets stop being
received. If this condition occurs, the LXT971A returns to the auto-negotiation phase if auto-
negotiation is enabled. If the Link Integrity Test function is disabled by setting Register bit
16.14 = 1 in the Configuration Register, the LXT971A transmits packets, regardless of link status.
10BASE-T SQE (Heartbeat)
By default, the Signal Quality Error (SQE) or heartbeat function is disabled on the LXT971A. To
enable this function, set Register bit 16.9 = 1. When this function is enabled, the LXT971A asserts
its COL output for 5-15 BT after each packet. See
parameters.
10BASE-T Jabber
If a transmission exceeds the jabber timer, the LXT971A disables the transmit and loopback
functions. See
The LXT971A automatically exits jabber mode after the unjabber time has expired. This function
can be disabled by setting Register bit 16.10 = 1.
10BASE-T Polarity Correction
The LXT971A automatically detects and corrects for the condition where the receive signal
(TPFIP/N) is inverted. Reversed polarity is detected if eight inverted link pulses, or four inverted
end-of-frame (EOF) markers, are received consecutively. If link pulses or data are not received by
the maximum receive time-out period (96-128 ms), the polarity state is reset to a non-inverted
state.
Monitoring Operations
Monitoring Auto-Negotiation
Auto-negotiation can be monitored as follows:
•
•
Register bit 17.7 is set to 1 once the auto-negotiation process is completed.
Register bits 1.2 and 17.10 are set to 1 once the link is established.
Figure 34 on page 67
for jabber timing parameters.
Figure 35 on page 67
for SQE timing
Rev. Date: August 7, 2002
Document #: 249414
Revision #: 002
Datasheet