IDT70V9269L15PRFI IDT [Integrated Device Technology], IDT70V9269L15PRFI Datasheet - Page 16

• Manufacturer Part Number: IDT70V9269L15PRFI
• Description: HIGH-SPEED 3.3V 32K x 16 SYNCHRONOUS DUAL-PORT STATIC RAM
• Manufacturer: IDT [Integrated Device Technology]

Timing Waveform of Write with Address Counter Advance
(Flow-Through or Pipelined Outputs)
NOTES:
1. CE
2. CE
3. The "Internal Address" is equal to the "External Address" when ADS = V
4. Addresses do not have to be accessed sequentially since ADS = V
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. ADDR
7. CNTEN = V
Timing Waveform of Counter Reset (Pipelined Outputs)
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
are shown here simply for clarification.
The ‘An +1’Address is written to during this cycle.
0
0
, UB, LB, and R/W = V
, UB, LB = V
INTERNAL
ADDRESS
ADDRESS
INTERNAL
ADDRESS
ADDRESS
DATA
CNTRST
DATA
CNTEN
DATA
CNTEN
IL
CLK
ADS
R/
OUT
ADS
CLK
advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance.
W
IN
IN
(3)
IL
(3)
; CE
(7)
(5)
1
t
= V
Ax
SRST
IL
(6)
t
t
IH
; CE
SAD
t
SA
SD
.
t
An
Dn
HRST
EXTERNAL
ADDRESS
t
1
t
CH2
t
t
WRITE
COUNTER
HAD
HD
HA
and CNTRST = V
t
CH2
RESET
t
CYC2
t
CYC2
t
CL2
An
t
t
t
SAD
SCN
t
t
SD
SW
(6)
CL2
(7)
D
Dn + 1
t
t
0
HCN
t
HAD
t
HW
HD
IH
WITH COUNTER
ADDRESS 0
.
WRITE
WRITE
0
IL
constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
Dn + 1
An + 1
COUNTER HOLD
IL
ADDRESS 0
and equals the counter output when ADS = V
6.42
READ
16
WRITE
(1)
Dn + 2
ADDRESS 1
READ
Industrial and Commercial Temperature Ranges
1
An + 2
t
SA
An
Q
Dn + 3
0
t
HA
WRITE WITH COUNTER
ADDRESS n
READ
An
IH
An + 3
(2)
.
(4)
An + 1
Q
Dn + 4
ADDRESS n+1
0
1
will be accessed. Extra cycles
READ
An + 1
An + 4
3743 drw 16
An + 2
3743 drw 17
Qn