IDT70V9269L15PRFI IDT [Integrated Device Technology], IDT70V9269L15PRFI Datasheet - Page 14

• Manufacturer Part Number: IDT70V9269L15PRFI
• Description: HIGH-SPEED 3.3V 32K x 16 SYNCHRONOUS DUAL-PORT STATIC RAM
• Manufacturer: IDT [Integrated Device Technology]

Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = V
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE
4. Addresses do not have to be accessed sequentially since ADS = V
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
reference use only.
0
, UB, LB, and ADS = V
ADDRESS
ADDRESS
DATA
DATA
DATA
DATA
UB, LB
UB, LB
CLK
R/
CE
CE
CLK
R/
OUT
CE
CE
OUT
OE
W
IN
W
IN
0
1
0
1
(4)
(4)
(2)
IL
(2)
; CE
t
t
t
t
t
t
SB
t
SC
SW
SA
t
SB
SW
SC
SA
An
1
An
, CNTEN, and CNTRST = V
t
t
t
t
t
t
HC
HW
t
t
HA
HB
HW
HC
HB
HA
t
t
CH1
t
t
CD1
CH1
CD1
t
t
CYC1
CYC1
READ
READ
t
t
CL1
CL1
Qn
Qn
An +1
An +1
t
t
DC
DC
t
CD1
t
OHZ
IH
.
(1)
IL
t
t
Qn + 1
SW
constantly loads the address on the rising edge of the CLK; numbers are for
An + 2
SD
Dn + 2
An + 2
t
t
HD
HW
6.42
14
NOP
t
CKHZ
(5)
(1)
WRITE
t
t
SW
SD
Dn + 2
An + 2
An + 3
Dn + 3
t
t
HD
HW
WRITE
Industrial and Commercial Temperature Ranges
An + 3
An + 4
t
CKLZ
t
OE
(1)
t
t
CD1
CD1
t
CKLZ
(1)
READ
READ
Qn + 3
Qn + 4
An + 4
An + 5
t
t
DC
DC
t
t
CD1
CD1
3743 drw 12
3743 drw 13
IL
)
(3)
(3)