IDT70V9269L15PRFI IDT [Integrated Device Technology], IDT70V9269L15PRFI Datasheet - Page 13

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IDT70V9269L15PRFI

Manufacturer Part Number
IDT70V9269L15PRFI
Description
HIGH-SPEED 3.3V 32K x 16 SYNCHRONOUS DUAL-PORT STATIC RAM
Manufacturer
IDT [Integrated Device Technology]
Datasheet
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = V
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE
4. Addresses do not have to be accessed sequentially since ADS = V
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
reference use only.
0
, UB, LB, and ADS = V
ADDRESS
DATA
ADDRESS
DATA
DATA
UB, LB
DATA
CLK
UB, LB
CE
CE
R/
OUT
OE
CLK
W
IN
CE
CE
R/
OUT
0
1
(4)
W
IN
0
1
(4)
t
IL
t
t
t
SB
SC
SW
SA
; CE
t
t
t
t
SB
SW
An
SC
SA
An
1
t
t
t
t
HC
HW
HA
HB
, CNTEN, and CNTRST = V
t
CH2
t
t
t
t
(2)
HW
HC
HB
HA
t
CH2
(2)
t
CYC2
t
READ
CYC2
t
CL2
t
READ
CL2
An +1
An +1
t
CD2
t
CD2
t
OHZ
Qn
(1)
IH
.
t
t
Dn + 2
SW
SD
IL
Qn
An + 2
t
SW
constantly loads the address on the rising edge of the CLK; numbers are for
An + 2
t
t
HD
HW
t
6.42
HW
13
NOP
t
CKHZ
(5)
WRITE
Dn + 3
An + 3
(1)
t
SD
Dn + 2
An + 2
t
HD
Industrial and Commercial Temperature Ranges
WRITE
An + 4
An + 3
t
CKLZ
(1)
t
CKLZ
READ
An + 5
(1)
READ
An + 4
t
CD2
t
CD2
IL
)
3743 drw 11
(3)
Qn + 4
Qn + 3
3743 drw 10
(3)

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