ADF4154 Analog Devices, ADF4154 Datasheet - Page 9

• Manufacturer Part Number: ADF4154
• Description: Fractional-n Frequency Synthesizer
• Manufacturer: Analog Devices

CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 17. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that the REF
power-down.
RF INPUT STAGE
The RF input stage is shown in Figure 18. It is followed by a
2-stage limiting amplifier to generate the current mode logic
(CML) clock levels needed for the prescaler.
RF INT DIVIDER
The RF INT CMOS counter allows a division ratio in the PLL
feedback counter. Division ratios from 31 to 511 are allowed.
INT, FRAC, MOD, AND R RELATIONSHIP
The INT, FRAC, and MOD values, in conjunction with the
R counter, make it possible to generate output frequencies that
are spaced by fractions of the phase frequency detector (PFD).
See the RF Synthesizer: A Worked Example section for more
information. The RF VCO frequency ( RF
where RF
controlled oscillator (VCO).
RF
RF
IN
IN
RF
A
B
OUT
OUT
REF
=
is the output frequency of the external voltage
IN
F
PFD
GENERATOR
NC
POWER-DOWN
SW1
Figure 17. Reference Input Stage
CONTROL
BIAS
×
(
NO
Figure 18. RF Input Stage
INT
NC
SW3
SW2
2kΩ
+
(
100kΩ
FRAC
1.6V
IN
BUFFER
pin is not loaded on
MOD
2kΩ
OUT
)
)
TO R COUNTER
) equation is
AGND
AV
DD
Rev. 0 | Page 9 of 20
(1)
where:
REF
D is the REF
R is the preset divide ratio of binary 4-bit programmable
reference counter (1 to 15).
INT is the preset divide ratio of binary 9-bit counter (31 to 511).
MOD is the preset modulus ratio of binary 12-bit program-
mable FRAC counter (2 to 4095).
FRAC is the preset fractional ratio of binary 12-bit
programmable FRAC counter (0 to MOD).
RF R COUNTER
The 4-bit RF R counter allows the input reference frequency
(REF
the PFD. Division ratios from 1 to 15 are allowed.
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 20 is a simplified schematic.
The PFD includes a fixed delay element that sets the width of
the antibacklash pulse, which is typically 3 ns. This pulse
ensures that there is no dead zone in the PFD transfer function
and gives a consistent reference spur level.
INPUT STAGE
+IN
–IN
IN
FROM RF
IN
F
is the reference input frequency.
PFD
) to be divided down to produce the reference clock to
HI
HI
=
REF
IN
D2
D1
CLR1
doubler bit.
CLR2
RF N-DIVIDER
U1
U2
IN
N COUNTER
Figure 20. PFD Simplified Schematic
Q1
Q2
×
REG
INT
Figure 19. A and B Counters
(
UP
DOWN
1
DELAY
+
D
)
R
U3
MOD
REG
N = INT + FRAC/MOD
INTERPOLATOR
THIRD ORDER
FRACTIONAL
CHARGE
VALUE
PUMP
FRAC
ADF4154
TO PFD
CP
(2)