ADF4154 Analog Devices, ADF4154 Datasheet - Page 15

• Manufacturer Part Number: ADF4154
• Description: Fractional-n Frequency Synthesizer
• Manufacturer: Analog Devices

REGISTER DEFINITION
N-Divider Register, R0
The on-chip N-divider register is programmed by setting
R0[1, 0] to [0, 0]. Table 8 shows the input data format for
programming this register.
9-Bit INT Value
These nine bits control what is loaded as the INT value. This is
used to determine the overall feedback division factor (see
Equation 1).
12-Bit FRAC Value
These 12 bits control what is loaded as the FRAC value into the
fractional interpolator. This value helps determine the overall
feedback division factor (see Equation 1). The FRAC value must
be less than the value loaded into the MOD register.
Fast-Lock
Setting the part to logic high enables fast-lock mode. To use
fast-lock, the required time value for wide bandwidth mode
needs to be loaded into the R-divider register.
The charge pump current increases from 16× the minimum
current and reverts back to 1× the minimum current once the
time value loaded has expired.
See the Fast-Lock Timer and Register Sequences section for
more information.
R-DIVIDER REGISTER, R1
The on-chip R-divider register is programmed by setting
R1[1, 0] to [0, 1]. Table 9 shows the input data format for
programming this register.
Load Control
When set to logic high, the value being programmed in the
modulus is not loaded into the modulus. Instead, it sets the fast-
lock timer. The value of the fast-lock timer/F
of time the PLL stays in wide bandwidth mode.
MUXOUT
The on-chip multiplexer is controlled by R1[22...20] on the
ADF4154. Table 9 shows the truth table.
Digital Lock Detect
The digital lock detect output goes high if there are 40
successive PFD cycles with an input error of less than 15 ns. It
stays high until a new channel is programmed or until the error
at the PFD input exceeds 30 ns for one or more cycles. If the
loop bandwidth is narrow compared to the PFD frequency, the
error at the PFD inputs may drop below 15 ns for 40 cycles
around a cycle slip. Therefore, the digital lock detect may go
falsely high for a short period until the error again exceeds
30 ns. In this case, the digital lock detect is reliable only as a
loss-of-lock detector.
PFD
is the amount
Rev. 0 | Page 15 of 20
Prescaler (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with the INT,
FRAC, and MOD counters, determines the overall division ratio
from the RF
takes the clock from the RF input stage and divides it down for
the counters. It is based on a synchronous 4/5 core. When set to
4/5, the maximum RF frequency allowed is 2 GHz. Therefore,
when operating the ADF4154 above 2 GHz, this must be set to
8/9. The prescaler limits the INT value.
The prescaler can also influence the phase noise performance. If
INT < 91, a prescaler of 4/5 should be used. For applications
where INT > 91, P = 8/9 should be used for optimum noise
performance (see Table 9).
4-Bit RF R Counter
The 4-bit RF R counter allows the input reference frequency
(REF
the phase frequency detector (PFD). Division ratios from 1 to
15 are allowed.
12-Bit Interpolator Modulus/Fast-Lock Timer
Bits DB13–DB2 have two functions depending on the value of
the load control bit: modulus or fast lock timer value.
When the load control bit = 0 (DB23), the required modulus
may be programmed into the R-divider register (DB13–DB2).
When the load control bit = 1 (DB23), the required fast-lock
timer value may be programmed into the R-divider register
(DB13–DB2).
This programmable register sets the fractional modulus, which
is the ratio of the PFD frequency to the channel step resolution
on the RF output. Refer to the RF Synthesizer: A Worked
Example section for more information.
The ADF4154 programmable modulus is double-buffered. This
means that two events must occur before the part uses a new
modulus value. First, the new modulus value is latched into the
device by writing to the R-divider register. Second, a new write
must be performed on the N-divider register. Therefore, when-
ever the modulus value is updated, the N-divider register must
be written to so that the modulus value is loaded correctly.
CONTROL REGISTER, R2
The on-chip control register is programmed by setting R2[1, 0]
to [0, 1]. Table 10 shows the input data format for programming
this register.
RF Counter Reset
DB3 is the RF counter reset bit for the ADF4154. When this is 1,
the RF synthesizer counters are held in reset. For normal
operation, this bit should be 0.
With P = 4/5, N
With P = 8/9, N
IN
) to be divided down to produce the reference clock to
IN
to the PFD input. Operating at CML levels, it
MIN
MIN
= 31.
= 91.
ADF4154