ADF4154 Analog Devices, ADF4154 Datasheet - Page 19

• Manufacturer Part Number: ADF4154
• Description: Fractional-n Frequency Synthesizer
• Manufacturer: Analog Devices

ADuC812 Interface
Figure 24 shows the interface between the ADF4154 and the
ADuC812 MicroConverter®. Since the ADuC812 is based on an
8051 core, this interface can be used with any 8051-based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, bring the I/O
port driving LE low. Each latch of the ADF4154 needs a 24-bit
word, which is accomplished by writing three 8-bit bytes from
the MicroConverter to the device. After the third byte is written,
the LE input should be brought high to complete the transfer.
When operating in the mode described, the maximum
SCLOCK rate of the ADuC812 is 4 MHz. This means that the
maximum rate at which the output frequency can be changed is
180 kHz.
ADSP-2181 Interface
Figure 25 shows the interface between the ADF4154 and the
ADSP-21xx digital signal processor. As discussed previously, the
ADF4154 needs a 24-bit serial word for each latch write. The
easiest way to accomplish this using the ADSP-21xx family is to
use the autobuffered transmit mode of operation with alternate
framing. This provides a means for transmitting an entire block
of serial data before an interrupt is generated. Set up the word
length for eight bits and use three memory locations for each
24-bit word. To program each 24-bit latch, store each of the
three 8-bit bytes, enable the autobuffered mode, and write to the
transmit register of the DSP. This last operation initiates the
autobuffer transfer.
ADuC812
I/O PORTS
SCLOCK
Figure 24. ADuC812 to ADF4154 Interface
MOSI
SCLK
SDATA
LE
MUXOUT
(LOCK DETECT)
ADF4154
Rev. 0 | Page 19 of 20
PCB DESIGN GUIDELINES FOR CHIP SCALE
PACKAGE
The lands on the chip scale package (CP-20) are rectangular.
The printed circuit board pad for these should be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. The land should be centered on the pad.
This ensures that the solder joint size is maximized.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edges of the pad pattern to avoid shorting.
Thermal vias may be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated into the thermal pad at
1.2 mm pitch grid. The via diameter should be between 0.3 mm
and 0.33 mm, and the via barrel should be plated with 1 oz. of
copper to plug the via.
The user should connect the printed circuit board thermal pad
to AGND.
ADSP-21xx
I/O FLAGS
Figure 25. ADSP-21xx to ADF4154 Interface
SCLOCK
TFS
DT
SCLK
SDATA
LE
MUXOUT
(LOCK DETECT)
ADF4154
ADF4154