ADF4154 Analog Devices, ADF4154 Datasheet - Page 17

• Manufacturer Part Number: ADF4154
• Description: Fractional-n Frequency Synthesizer
• Manufacturer: Analog Devices

For example, in a GSM 1800 system, where a 1.8 GHz RF
frequency output (RF
frequency input (REF
resolution (f
From Equation 4,
MODULUS
The choice of modulus (MOD) depends on the reference signal
(REF
the RF output. For example, a GSM system with 13 MHz REF
would set the modulus to 65, resulting in the RF output resolu-
tion (f
REFERENCE DOUBLER AND REFERENCE DIVIDER
The reference doubler on-chip allows the input reference signal
to be doubled. This is useful for increasing the PFD comparison
frequency. Making the PFD frequency higher improves the
noise performance of the system. Doubling the PFD frequency
usually results in an improvement in noise performance of 3 dB.
It is important to note that the PFD cannot be operated above
32 MHz due to a limitation in the speed of the Σ-Δ circuit of
the N divider.
12-BIT PROGRAMMABLE MODULUS
Unlike most other fractional-N PLLs, the ADF4154 allows the
user to program the modulus over a 12-bit range. This means
that the user can set up the part in many different configura-
tions for the application, when combined with the reference
doubler and the 4-bit R counter.
For example, consider an application that requires a 1.75 GHz
RF and a 200 kHz channel step resolution. The system has a
13 MHz reference signal.
One possible setup is feeding the 13 MHz directly to the PFD
and programming the modulus to divide by 65, which would
result in the required 200 kHz resolution.
Another possible setup is using the reference doubler to create
26 MHz from the 13 MHz input signal. The 26 MHz signal is
then fed into the PFD, which programs the modulus to divide
by 130. This setup also results in 200 kHz resolution and offers
superior phase noise performance over the previous setup.
The programmable modulus is also very useful for multi-
standard applications. If a dual-mode phone requires PDC and
GSM 1800 standards, the programmable modulus is a huge
benefit. The PDC requires a 25 kHz channel step resolution,
whereas the GSM 1800 requires a 200 kHz channel step
F
1
INT
PFD
8 .
IN
MOD
MOD
G
RES
) available and the channel resolution (f
= [13 MHz × (1 + 0)/1] = 13 MHz
=
=
) of 200 kHz (13 MHz/65) that is necessary for GSM.
138
13
=
=
RES
MHz
;
13
REF
≥
) is required on the RF output.
MHz
FRAC
IN
×
(
OUT
INT
IN
f
RES
200
=
) is available and a 200 kHz channel
) is required, a 13 MHz reference
30
+
kHz
FRAC
=
65
65
)
≥
RES
) required at
Rev. 0 | Page 17 of 20
IN
(5)
(6)
resolution. A 13 MHz reference signal could be fed directly to
the PFD. The modulus would be programmed to 520 when in
PDC mode (13 MHz/520 = 25 kHz). The modulus would be
reprogrammed to 65 for GSM 1800 operation (13 MHz/65 =
200 kHz). It is important that the PFD frequency remains con-
stant (13 MHz). By keeping the PFD constant, the user can
design a one-loop filter that can be used in both setups without
running into stability issues. The ratio of the RF frequency to
the PFD frequency affects the loop design. Keeping this
relationship constant instead of changing the modulus factor
results in a stable filter.
SPURIOUS OPTIMIZATION AND FAST-LOCK
The ADF4154 can be optimized for low spurious signals by
using the noise and spur register. However, in order to achieve
fast-lock time, a wider loop bandwidth is needed. Note that a
wider loop bandwidth can lead to notable spurious signals,
which cannot be reduced significantly by the loop filter.
Using the fast-lock feature can achieve the same fast-lock time
as the noise and spur register, but with the advantage of lower
spurious signals, since the final loop bandwidth is reduced by
a quarter.
FAST-LOCK TIMER AND REGISTER SEQUENCES
If the fast-lock mode is used, a timer value needs to be loaded
into the PLL to determine the time of the wide bandwidth.
When the load control bit = 1, the timer value is loaded via the
12-bit modulus value. To use fast-lock, the PLL must be written
to in the following sequence:
1.
2.
3.
4.
5.
Once this procedure is completed, future frequency jumps
deploying fast-lock need to repeat only Step 5.
Load the R-divider register with DB23 = 1 and the chosen
fast-lock timer value (DB13–DB2) instead of the modulus.
Note that the duration of time the PLL remains in wide
bandwidth is equal to the fast-lock timer/F
Load the noise and spur register .
Load the control register .
Load R-divider register with DB23 = 0 and MUXOUT =
110 (DB22–DB20). All the other needed parameters,
including the modulus, also need to be loaded.
Load the N-divider register , including fast-lock = 1
(DB23), to activate fast-lock mode.
PFD
.
ADF4154