lrs1830 Sharp Microelectronics of the Americas, lrs1830 Datasheet - Page 27
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lrs1830
Manufacturer Part Number
lrs1830
Description
Stacked Chip 256m X16 Boot Block Flash And 32m X16 Scram
Manufacturer
Sharp Microelectronics of the Americas
Datasheet
1.LRS1830.pdf
(82 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LRS1830
Manufacturer:
SHARP
Quantity:
6 236
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Part Number:
LRS1830
Manufacturer:
FAIRCHILD
Quantity:
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6.6 AC Electrical Characteristics for Flash Memory
6.6.1 AC Test Conditions
Notes:
6.6.2 Read Cycle
Notes:
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing Ref. level
Output Load
t
t
1. The capacitance in a chip is not included.
t
1. Sampled, not 100% tested.
2. OE may be delayed up to t
3. Address setup time (t
4. Address hold time (t
5. Specifications t
6. Specifications t
t
EHQZ
ELAX
AVEL
EHEL
Symbol
t
t
t
t
t
t
t
t
t
t
t
operations.
sharp
AVQV
BLQV
GLQV
PHQV
GLQX
AVBV
BVAX
BVBV
ELQV
t
ELQX
AVAV
t
APA
OH
, t
, t
, t
, t
GHGL
GHQZ
AVGL
GLAX
Read Cycle Time
Address to Output Delay
BS to Output Delay
F-CE to Output Delay
Page Address Access Time
OE to Output Delay
F-RST High to Output Delay
F-CE or OE to Output in High-Z, Whichever Occurs First
F-CE to Output in Low-Z
OE to Output in Low-Z
Output Hold from First Occurring Address, F-CE or OE Change
Address Setup to F-CE and OE Going Low
for Reading Status Register
Address Hold from F-CE and OE Going Low
for Reading Status Register
F-CE and OE Pulse Width High for Reading Status Register
Address Setup to BS (Bank Select)
for Reading Status Register
Address Hold from BS (Bank Select)
for Reading Status Register
BS Pulse Width High for Reading Status Register
AVBV
AVEL
(1)
ELAX
, t
, t
AVEL
BVAX
AVGL
, t
, t
ELQV
GLAX
AVGL
and t
, t
ELAX
) is defined from the falling edge of F-CE or OE (whichever goes low last).
BVBV
) is defined from the falling edge of F-CE or OE (whichever goes low last).
t
GLQV
, t
GLAX
for read operations apply to only status register read operations.
Parameter
after the falling edge of F-CE without impact to t
and t
EHEL
L R S1 8 3 0
, t
GHGL
1TTL +C
0 V to 2.7 V
1/2 V
for read operations apply to only status register read
5 ns
L
CC
(50pF)
(T
A
= -30°C to +85°C, V
Notes
3,5
4,5
2
2
1
1
1
1
5
6
6
6
ELQV
Min.
70
10
30
10
30
20
20
0
0
0
.
CC
Max.
150
70
70
70
35
20
20
= 2.7V to 3.1V)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
24