lrs1830 Sharp Microelectronics of the Americas, lrs1830 Datasheet - Page 13

• Manufacturer Part Number: lrs1830
• Description: Stacked Chip 256m X16 Boot Block Flash And 32m X16 Scram
• Manufacturer: Sharp Microelectronics of the Americas

6.2 Command Definitions for Flash Memory
6.2.1 Command Definitions
Notes:
Read Array
Read Identifier Codes
Read Query
Read Status Register
Clear Status Register
Block Erase
Bank Erase
Program
Page Buffer Program
Block Erase and (Page Buffer)
Program Suspend
Block Erase and (Page Buffer)
Program Resume
Set Block Lock Bit
Clear Block Lock Bit
Set Block Lock-down Bit
Set Partition Configuration
Register
1. Bus operations are defined in 6.1.1 Bus Operation.
2. All addresses which are written at the first bus cycle should be the same as the addresses which are written at the second
3. ID=Data read from identifier codes (See 6.2.2 Identifier Codes for Read Operation).
4. Following the Read Identifier Codes command, read operations access manufacturer code, device code, block lock
5. Block erase, bank erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked block
6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup.
7. Following the third bus cycle, input the program sequential address and write data of “N” times. Finally, input the any
bus cycle.
X=Any valid address within the device. Bank erase is executed to the bank selected by BS.
PA=Address within the selected partition.
IA=Identifier codes address (See 6.2.2 Identifier Codes for Read Operation).
QA=Query codes address. Refer to the LH28F320BF, LH28F640BF, LH28F128BF series Appendix for details.
BA=Address within the block being erased, set/cleared block lock bit or set block lock-down bit.
WA=Address of memory location for the Program command or the first address for the Page Buffer Program command.
PCRC=Partition configuration register code presented on the address A
QD=Data read from query database. Refer to the LH28F320BF, LH28F640BF, LH28F128BF series Appendix for details.
SRD=Data read from status register. See 6.3 Register Definition for a description of the status register bits.
WD=Data to be programmed at location WA. Data is latched on the rising edge of WE or CE (whichever goes high first)
N-1=N is the number of the words to be loaded into a page buffer.
configuration code, partition configuration register code (See 6.2.2 Identifier Codes for Read Operation).
The Read Query command is available for reading CFI (Common Flash Interface) information.
can be erased or programmed when F-RST is V
valid address within the target block to be programmed and the confirm command (D0H). Refer to the LH28F320BF,
LH28F640BF, LH28F128BF series Appendix for details.
sharp
during command write cycles.
Command
Cycles
Req’d
Bus
1
2
1
2
2
2
1
1
2
2
2
2
2
2
4
(11)
Notes
5, 9
5, 6
5, 7
8, 9
8, 9
10
12
4
4
5
IH
.
L R S1 8 3 0
Oper
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
(1)
First Bus Cycle
Address
PCRC
WA
WA
BA
BA
BA
BA
PA
PA
PA
PA
PA
PA
PA
X
(2)
0
-A
15
40H or
.
D0H
Data
FFH
E8H
B0H
90H
98H
70H
50H
20H
30H
10H
60H
60H
60H
60H
Oper
Write
Write
Write
Write
Write
Write
Write
Write
Read
Read
Read
(1)
Second Bus Cycle
Address
PCRC
WA
WA
QA
BA
BA
BA
BA
PA
IA
X
(2)
Data
SRD
D0H
D0H
D0H
01H
2FH
04H
WD
N-1
QD
ID
(3)
10