zl50212 Zarlink Semiconductor, zl50212 Datasheet - Page 6

• Manufacturer Part Number: zl50212
• Description: 288 Channel Voice Echo Canceller
• Manufacturer: Zarlink Semiconductor

6
ZL50212
Sout1,Sout2,Sout3,
Sout4,Sout5,Sout6,
Sout7,Sout8,Sout9
DTA1, DTA2, DTA3,
DTA4, DTA5, DTA6,
DTA7, DTA8, DTA9
IRQ1, IRQ2, IRQ3,
IRQ4, IRQ5, IRQ6,
IRQ7, IRQ8, IRQ9
Signal Name
MCLK
ODE
R/W
Fsel
C4i
F0i
DS
Signals
Signals
Signal
Signals
Signal
Signal
Signal
Signal
Signal
Signal
Signal
Type
User
User
User
User
User
User
User
User
User
User
AJ6,AG23,L30,L29,
AF9,W30,C29,D30,
N2,AK28,N1,AK6,
N4,AJ26,N3,AK5,
B7,W27,A7,AH8,
AJ7,AK27,M28,
BGA Ball #
M27,AK16
AK15
M29
Zarlink Semiconductor Inc.
B13
K29
V29
B26
B25
A16
A15
Send PCM Signal Outputs (Outputs). Port 1 TDM
data output streams. Each Sout pin outputs serial TDM
data streams at 2.048 Mb/s with 32 channels per
stream.
Data Strobe (Input). This active low input works in
conjunction with CS to enable the read and write
operations. This signal is connected to all processors.
Read/Write (Input). This input controls the direction of
the data bus lines (D7-D0) during a microprocessor
access. This signal is connected to all processors.
Data Transfer Acknowledgment (Open Drain
Output). These active low outputs indicate that a data
bus transfer is completed. A pull-up resistor (1K
typical) is required at these outputs.
Output Drive Enable (Input). This input pin is
logically AND’d with the ODE bit-6 of the Main Control
Register. When both ODE bit and ODE input pin are
high, the Rout and Sout ST-BUS outputs are enabled.
When the ODE bit is low or the ODE input pin is low,
the Rout and Sout ST-BUS outputs are high
impedance. This signal is connected to all processors.
Frame Pulse (Input). This input accepts and
automatically identifies frame synchronization signals
formatted according to ST-BUS or GCI interface
specifications.This signal is connected to all
processors.
Serial Clock (Input). 4.096 MHz serial clock for
shifting data in/out on the serial streams (Rin, Sin,
Rout, Sout).This signal is connected to all processors.
Frequency select (Input). This input selects the Mas-
ter Clock frequency operation. When Fsel pin is low,
nominal 20MHz Master Clock input must be applied.
When Fsel pin is high, nominal 10MHz Master Clock
input must be applied.This signal is connected to all
processors.
Master Clock (Input). Nominal 10MHz or 20MHz
Master Clock input. May be connected to an
asynchronous (relative to frame signal) clock
source.This signal is connected to all processors.
Interrupt Request (Open Drain Output). These
outputs go low when an interrupt occurs in any
channel. Each IRQ returns high when all the interrupts
have been read from the Interrupt FIFO Register of
respective EVP. A pull-up resistor (1K typical) is
required at these outputs.
Signal Description
Data Sheet