zl50212 Zarlink Semiconductor, zl50212 Datasheet - Page 29

• Manufacturer Part Number: zl50212
• Description: 288 Channel Voice Echo Canceller
• Manufacturer: Zarlink Semiconductor

Data Sheet
Note: In order to correctly write to Control Register 1 and 2 of ECB, it is necessary to write the data twice to the register, one
immediately after another. The two writes must be separated by at least 350ns and no more than 20us.
Reserve
Reserve
Reserve
Reserve
Reserve
HPFDis
NLPDis
AutoTD
MuteS
MuteR
DTDet
PHDis
NBDis
TDis
TDis
TDG
Bit 7
Bit 7
NB
TD
Power-up
Power-up
00
00
hex
hex
When high, tone detection is disabled. When low, tone detection is enabled. When both
Echo Cancellers A and B TDis bits are high, Tone Disable processors are disabled
entirely and are put into Power Down mode.
When high, the tone detectors will trigger upon the presence of a 2100 Hz tone regardless
of the presence/absence of periodic phase reversals. When low, the tone detectors will
trigger only upon the presence of a 2100 Hz tone with periodic phase reversals.
When high, the non-linear processor is disabled. When low, the non-linear processors
function normally. Useful for G.165 conformance testing.
When high, the echo canceller puts itself in Bypass mode when the tone detectors detect
the presence of 2100 Hz tone. See PHDis for qualification of 2100 Hz tones.
When low, the echo canceller algorithm will remain operational regardless of the state of
the 2100 Hz tone detectors.
When high, the narrow-band detector is disabled. When low, the narrow-band detector is
enabled.
When high, the offset nulling high pass filters are bypassed in the Rin and Sin paths.
When low, the offset nulling filters are active and will remove DC offsets on PCM input
signals.
When high, data on Sout is muted to quiet code. When low, Sout carries active code.
When high, data on Rout is muted to quiet code. When low, Rout carries active code.
Reserved bit.
Logic high indicates the presence of a 2100Hz tone.
Logic high indicates the presence of a double-talk condition.
Reserved bit.
Reserved bit.
Reserved bit.
Tone detection status bit gated with the AutoTD bit (Control Register 2).
Logic high indicates that AutoTD has been enabled and the tone detector has detected
the presence of a 2100Hz tone.
Logic high indicates the presence of a narrow-band signal on Rin.
PHDis
Bit 6
Bit 6
TD
NLPDis
DTDet
Bit 5
Bit 5
Functional Description of Register Bits
Functional Description of Register Bits
ECA: Control Register 2
ECB: Control Register 2
ECA: Status Register
ECB: Status Register
Reserve
AutoTD
Zarlink Semiconductor Inc.
Bit 4
Bit 4
Reserve
NBDis
Bit 3
Bit 3
Reserve
HPFDis
Bit 2
Bit 2
01
21
02
22
MuteS
hex
hex
hex
hex
TDG
Bit 1
Bit 1
R/W Address:
R/W Address:
R/W Address:
R/W Address:
+ Base Address
+ Base Address
+ Base Address
+ Base Address
MuteR
ZL50212
Bit 0
Bit 0
NB
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