zl50212 Zarlink Semiconductor, zl50212 Datasheet - Page 17

• Manufacturer Part Number: zl50212
• Description: 288 Channel Voice Echo Canceller
• Manufacturer: Zarlink Semiconductor

Data Sheet
5.0
The throughput delay of the EVP varies according to the device configuration. For all device configurations, Rin to
Rout has a delay of two frames and Sin to Sout has a delay of three frames. In Bypass state, the Rin to Rout and
Sin to Sout paths have a delay of two frames.
6.0
There are four TDM I/O streams, each with channels numbered from 0 to 31. One input stream is for Receive (Rin)
channels, and the other input stream is for Send (Sin) channels. Likewise, two output streams is for Rout PCM
channels, and Sout PCM channels. See Figure 9 for channel allocation.
6.1
The ZL50212 provides ST-BUS and GCI interface timing. The Serial Interface clock frequency, C4i, is 4.096 MHz.
The input and output data rate of the ST-BUS and GCI bus is 2.048 Mb/s.
The 8 KHz input frame pulse can be in either ST-BUS or GCI format. The EVP automatically detects the presence
of an input frame pulse and identifies it as either ST-BUS or GCI. In ST-BUS format, every second falling edge of
the C4i clock marks a bit boundary, and the data is clocked in on the rising edge of C4i, three quarters of the way
into the bit cell (See Figure 11). In GCI format, every second rising edge of the C4i clock marks the bit boundary,
and data is clocked in on the second falling edge of C4i, half the way into the bit cell (see Figure 12).
Note: Refer to Figure 11 and Figure 12 for timing details.
F0i
ST-BUS
F0i
GCI interface
Rin/Sin
Rout/Sout
Figure 9 - ST-BUS and GCI Interface Channel Assignment for 2Mb/s Data Streams
Echo Voice Processor (EVP) Throughput Delay
Serial PCM I/O channels
Serial Data Interface Timing
Channel 0
Zarlink Semiconductor Inc.
Channel 1
125 µsec
Channel 30
Channel 31
ZL50212
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