zl50212 Zarlink Semiconductor, zl50212 Datasheet - Page 22

• Manufacturer Part Number: zl50212
• Description: 288 Channel Voice Echo Canceller
• Manufacturer: Zarlink Semiconductor

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8.0
The EVP JTAG interface conforms to the Boundary-Scan standard IEEE1149.1. This standard specifies a
design-for-testability technique called Boundary-Scan test (BST). The operation of the Boundary Scan circuitry is
controlled by an Test Access Port (TAP) controller. JTAG inputs are 3.3 Volts compliant only.
8.1
The TAP provides access to many test functions of the EVP. It consists of four input pins and one output pin. The
following pins are found on the TAP.
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8.2
In accordance with the IEEE 1149.1 standard, the EVP uses public instructions. The JTAG Interface contains a 3-bit
instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP Controller
is in its shifted-IR state. Subsequently, the instructions are decoded to achieve two basic functions: to select the test
data register that will operate while the instruction is current, and to define the serial test data register path, which is
used to shift data between TDI and TDO during data register scanning.
8.3
As specified in IEEE 1149.1, each of the Echo Voice Processor’s JTAG Interface contains three test data registers:
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ZL50212
Test Clock Input (TCK)
The TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus
remains independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells
concurrent with the operation of the device and without interfering with the on-chip logic.
Test Mode Select Input (TMS)
The logic signals received at the TMS input are interpreted by the TAP Controller to control the test
operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to
V
Test Data Input (TDI)
Serial input data applied to this port is fed either into the instruction register or into a test data register,
depending on the sequence previously applied to the TMS input. Both registers are described in a
subsequent section. The received input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to V
Test Data Output (TDO)
Depending on the sequence previously applied to the TMS input, the contents of either the instruction
register or data register are serially shifted out towards the TDO. The data from the TDO is clocked on the
falling edge of the TCK pulses. When no data is shifted through the Boundary Scan cells, the TDO driver is
set to a high impedance state.
Test Reset (TRST)
This pin is used to reset the JTAG scan structure. This pin is internally pulled to V
Boundary-Scan register
The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path
around the boundary of each EVP core logic.
Bypass Register
The Bypass register is a single stage shift register that provides a one-bit path from TDI to TDO.
Device Identification register
The Device Identification register provides access to the following encoded information:
device version number, part number and manufacturer's name.
DD1
when it is not driven from an external source.
JTAG Support
Test Access Port (TAP)
Instruction Register
Test Data Registers
DD1
when it is not driven from an external source.
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Data Sheet