zl50212 Zarlink Semiconductor, zl50212 Datasheet
zl50212
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zl50212 Summary of contents
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... Features • ZL50212 has nine Echo Voice Processors in a single BGA package. This single device provides 288 channels of 64 msec echo cancellation or 144 channels at 128 msec echo cancellation • Each Echo Voice Processor has the capability of cancelling echo over 32 channels • ...
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... ZL50212 V Rin Serial to Parallel Sin MCLK Fsel PLL C4i Timing F0i Unit Figure 2 - Single Echo Voice Processor (EVP) Overview Features of Echo Voice Processor (EVP) • Each EVP can cancel echo tails of 64ms (32 channels) to 128ms (16 channels) with the ability to mix channels at 128ms or 64ms in any combination • ...
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... BGA BALL GRID ARRAY Figure 3 - 535 Ball BGA Ball Grid Array Zarlink Semiconductor Inc ZL50212 ...
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... ZL50212 Pin Description Signal Signal Name Type V = 3.3V Power DD1 (V ) DD_IO V = 1.8V Power DD2 (V ) DD_Core VSS Power TE1, TE2, TE3, TE4, TE5, TE6, Test Mode TE7, TE8, Pins TE9 OUTPUT Test TEST PINS pins 4 BGA Ball # AC5,AC26,AC27,AD26,AD5,AE5,AF12,AF13,AF1 4,AF17,AF18,AF19,AF24,AF6,AF7,AF8,AG24,AH 24,E13,E14,E17,E18,E19,E23,E24,E25,E6,E7,E8, F5,G26,G27,G5,H26,H5,M26,M5,N26,N5,P26,P27 ...
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... Receive PCM Signal Outputs (Outputs). Port 2 TDM AG8,V28,C26,C30, data output streams. Each Rout pin outputs serial TDM data streams at 2.048 Mb/s with 32 channels per C13 stream. Zarlink Semiconductor Inc. ZL50212 Signal Description Internal Connection. Connected to VSS for normal operation. Internal Connection. Connected to VSS for normal operation ...
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... ZL50212 Signal Signal Name Type Sout1,Sout2,Sout3, User Sout4,Sout5,Sout6, Signals Sout7,Sout8,Sout9 User DS Signal User R/W Signal DTA1, DTA2, DTA3, User DTA4, DTA5, DTA6, Signals DTA7, DTA8, DTA9 User Signal ODE User Signal F0i User C4i Signal User Signal Fsel User MCLK Signal User ...
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... DD2 C24, AE27 J3,W2,H2,AF4, PLL Ground. Must be connected to VSS. AF3,AF27,D24, C25,AF26,H1,W4, J2, AH1,AG3,AF22, D25,E27,AF21 D1,AH26,E1,AE1, Internal Connection. Connected to VSS for normal AD4,AK22,D18, operation. C18,U3 F2,AG25,G3,AF1, Internal Connection. Connected to VSS for normal AD3,AF25,B18, operation. A18,V2 Zarlink Semiconductor Inc. ZL50212 Signal Description 7 ...
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... Signals DT8,DT9 AT1, AT2, AT3, AT4, PLL Test AT5, AT6, AT7, AT8,AT9 Signals The following description applies to a single EVP (Echo Voice Processor). Note that the ZL50212 contains nine EVP’s. 8 BGA Ball # G4,AJ25,F1,AE2, Internal Connection. Connected to VSS for normal AG1,AH25,B17, operation ...
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... Level Adjust Echo Canceller (N), where 0 < N < 31 Zarlink Semiconductor Inc -12dB Linear/ Level Adjust µ/A-Law Microprocessor MuteS Interface Double - Talk Path Change Detector Detector Disable Tone MuteR Detector Offset µ/A-Law/ Null Linear ZL50212 Sout (channel N) ST-BUS PORT1 Rin (channel N) 9 ...
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... ZL50212 1.1 Adaptive Filter The adaptive filter adapts to the echo path and generates an estimate of the echo signal. This echo estimate is then subtracted from Sin. For each group of echo cancellers, the adaptive filter is a 1024 tap FIR adaptive filter which is divided into two sections. Each section contains 512 taps providing 64ms of echo estimation. In Normal configuration, the first section is dedicated to channel A and the second section to channel B ...
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... Register or Bit(s) NLPSel (Control Register 3) NLRun1 (Control Register 3) NLRun2 (Control Register 3) InjCtrl (Control Register 3) NLInc (Noise Control) Noise Scaling Table 1 - Comparison of NLP Types Zarlink Semiconductor Inc. ZL50212 Advanced Original NLP NLP Default Default Value Value 1 0 (feature not supported (feature ...
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... ZL50212 The NLInc sub-register in Noise Control is used to set the ramping speed. When InjCtrl = 1 (such as with the Advanced NLP), a lower value will give faster ramping. When InjCtrl = 0 (such as with the original NLP), a higher value will give faster ramping. NLInc is a 4-bit value, so only values from 0 to F(hex) are valid. ...
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... The ZL50212 has been certified G.168 (1997), (2000) and (2002) compliant in all 64 ms cancellation modes (i.e. Normal and Back-to-Back configurations) by in-house testing with the DSPG ECT-1 echo canceller tester. The ZL50212 has also been tested for G.168 compliance and all voice quality tests at AT&T Labs. The ZL50212 was classified as “carrier grade” echo canceller. ...
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... ZL50212 3.0 EVP Configuration The EVP architecture contains 32 echo cancellers divided into 16 groups. Each group has two echo cancellers which can be individually controlled (Echo Canceller A (ECA) and Echo Canceller B (ECB). They can be set in three distinct configurations: Normal, Back-to-Back, and Extended Delay. See Figures 6, 7, and 8. ...
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... Register 1, Bit 0 must always be set to zero. Table 4 shows the 16 groups of 2 cancellers that can each be configured into 64ms or 128ms echo tail capacity. channel A Sin + - echo Adaptive Filter path A (128 ms) channel A Rout PORT2 ECA Figure 8 - Extended Delay Configuration (128ms) Zarlink Semiconductor Inc. ZL50212 Sout Rin PORT1 15 ...
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... ZL50212 4.0 Echo Canceller Functional States Each echo canceller has four functional states: Mute, Bypass, Disable Adaptation and Enable Adaptation. 4.1 Mute In Normal and in Extended Delay configurations, writing a “1” into the MuteR bit replaces Rin with quiet code which is applied to both the Adaptive Filter and Rout. Writing a “1” into the MuteS bit replaces the Sout PCM data with quiet code ...
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... Serial Data Interface Timing The ZL50212 provides ST-BUS and GCI interface timing. The Serial Interface clock frequency, C4i, is 4.096 MHz. The input and output data rate of the ST-BUS and GCI bus is 2.048 Mb/s. The 8 KHz input frame pulse can be in either ST-BUS or GCI format. The EVP automatically detects the presence of an input frame pulse and identifies it as either ST-BUS or GCI ...
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... ZL50212 Base Address + MS LS Byte Byte - 00 hex - 01 hex - 02 hex - 03 hex - 04 hex - 05 hex - 06 hex - 07 hex - 08 hex - 09 hex - 0A hex - 0B hex 0D 0C hex hex 0F 0E hex hex 11 10 hex hex 13 12 hex hex 15 14 hex hex 17 16 hex hex 19 18 hex hex 1B 1A hex ...
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... Group Table 4 - Group and Channel allocation Zarlink Semiconductor Inc. ZL50212 to 0BF and interfaces to PCM hex hex Channels 16, 17 18, 19 20, 21 22, 23 24, 25 26, 27 28 ...
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... ZL50212 Group 0 Echo Cancellers Registers Group 1 Echo Cancellers Registers Groups 2 --> 14 Echo Cancellers Registers Group 15 Echo Cancellers Registers 7.4 Power Up Sequence On power up, the RESET pin must be held low for 100 µs. Forcing the RESET pin low will put each EVP in power down state. In this state, all internal clocks are halted, D<7:0>, Sout, Rout, DTA and IRQ pins are tristated. The 16 Main Control Registers, the Interrupt FIFO Register and the Test Register are reset to zero. When the RESET pin returns to logic high and a valid MCLK is applied, the user must wait 500 µ ...
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... The MIRQ bit 5 in the Main Control Register 0 masks interrupts from the EVP. To provide more flexibility, the MTDBI (bit-4) and MTDAI (bit-3) bits in the Main Control Register<15:0> allow Tone Disable to be masked or unmasked from generating an interrupt on a per channel basis. Refer to the Registers Description section. Zarlink Semiconductor Inc. ZL50212 21 ...
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... ZL50212 8.0 JTAG Support The EVP JTAG interface conforms to the Boundary-Scan standard IEEE1149.1. This standard specifies a design-for-testability technique called Boundary-Scan test (BST). The operation of the Boundary Scan circuitry is controlled by an Test Access Port (TAP) controller. JTAG inputs are 3.3 Volts compliant only. 8.1 Test Access Port (TAP) The TAP provides access to many test functions of the EVP ...
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... DD2 V IH3 V IH5 V IL Zarlink Semiconductor Inc. Symbol Min Max V -0.5 5.0 DD_IO -0.5 2.5 DD_CORE 0 DD1 0 -55 150 S ‡ Min Typ Max -40 +85 3.0 3.3 3.6 1.6 1.8 2.0 0.7V V DD1 DD1 0.7V 5.5 DD1 0.3V DD1 ZL50212 Units °C . Units ° ...
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... ZL50212 DC Electrical Characteristics Characteristics Static Supply Current 1 IDD_IO (V = 3.3V) DD1 Single EV Processor IDD_CORE (V DD2 Single EV Processor I 2 Power Consumption Input High Voltage S 4 Input Low Voltage 5 Input Leakage Input Leakage on Pullup Input Leakage on Pulldown 6 Input Pin Capacitance 7 Output High Voltage ...
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... RWH t 0 ADH t DDR t 3 DHR t 0 DSW t 0 DHW t AKD t 0 AKH t 20 IRD Zarlink Semiconductor Inc. ZL50212 Units Test Conditions unless otherwise stated. SS Units Notes MHz MHz ns ns Max Units Test Conditions ...
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... ZL50212 F0i C4i Rout/Sout Bit 0, Channel 31 Rin/Sin Bit 0, Channel 31 F0i C4i Sout/Rout Bit 7, Channel 31 Sin/Rin Bit 7, Channel 31 MCLK 26 t FPW FPS FPH t SOD Bit 7, Channel 0 Bit 6, Channel SIS SIH Bit 7, Channel 0 Bit 6, Channel 0 Figure 11 - ST-BUS Timing at 2.048 Mb/s t FPW ...
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... A0-A12 D0-D7 READ D0-D7 WRITE DTA IRQ Figure 15 - Motorola Non-Multiplexed Bus Timing t CSS t RWS t ADS VALID ADDRESS t DDR VALID READ DATA t DSW VALID WRITE DATA t AKD t IRD Zarlink Semiconductor Inc. ZL50212 CSH RWH ADH DHR DHW AKH V ...
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... ZL50212 9.0 EVP Registers Description Echo Canceller A (ECA): Control Register 1 Power-up 00 Bit 7 Bit 6 Reset INJDis Reset When high, the power-up initialization is executed. This presets all register bits including this bit and clears the Adaptive Filter coefficients. INJDis When high, the noise injection process is disabled. When low noise injection is enabled. ...
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... NLPDis AutoTD NBDis Functional Description of Register Bits ECA: Status Register ECB: Status Register Bit 5 Bit 4 Bit 3 DTDet Reserve Reserve Functional Description of Register Bits Zarlink Semiconductor Inc. ZL50212 R/W Address Base Address hex R/W Address Base Address hex Bit 2 Bit 1 Bit 0 HPFDis MuteS MuteR ...
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... ZL50212 Power-up 00 hex Bit 7 Bit 6 FD7 FD6 Power-up 00 hex Bit 7 Bit 6 NS7 NS6 Power-up 00 hex Bit 7 Bit Note: Bits marked with “0” are reserved bits and should be written “0” Amplitude of MU 1.0 Flat Delay (FD 7-0 - ECA: Flat Delay Register (FD) ...
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... The start of the exponential decay is defined as: Filter 2 Step Size (SS)] where 7-0 =4 and SSC =4, then the exponential decay start value is 512 - [NS 2-0 Zarlink Semiconductor Inc. - then MU=2 for the first 40 taps of the 7-0 ≤ normal mode and 0 ≤ FD 7-0 . hex ZL50212 -16 ). The ≤ 128 7-0 SSC . 2-0 x SS] = 7-0 31 ...
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... ZL50212 Power-up FB hex Bit 7 Bit 6 NLRun2 InjCtrl NLRun2 When high, the comfort noise level estimator actively rejects double-talk as being background noise. When low, the noise level estimator makes no such distinction. InjCtrl Selects which noise ramping scheme is used. See Table below. NLRun1 When high, the comfort noise level estimator actively rejects uncancelled echo as being background noise ...
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... Bit 2 Bit 1 Slow2 Slow1 Slow as compared to R/W Address Base Address hex R/W Address Base Address hex Bit 1 NS1 R/W Address Base Address hex R/W Address Base Address hex Bit 2 Bit 1 NLInc2 NLInc1 hex is recommended if InjCtrl = 0. ZL50212 Bit 0 Slow0 Bit 0 NS0 Bit 0 NLInc0 will provide 33 ...
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... ZL50212 ECA: Rin Peak Detect Register 2 (RP) Power-up N/A ECB: Rin Peak Detect Register 2 (RP) Bit 7 Bit 6 Bit 5 RP15 RP14 RP13 Power-up N/A Bit 7 Bit 6 Bit 5 RP7 RP6 RP5 These peak detector registers allow the user to monitor the receive in (Rin) peak signal level. The information is in 16-bit 2’ ...
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... Register 2 Bit 4 Bit 3 DTDT12 DTDT11 Register 1 Register 1 Bit 4 Bit 3 DTDT4 DTDT3 Functional Description of Register Bits = 0.5625 or -5 dB. The maximum value is 7FFF hex Zarlink Semiconductor Inc. ZL50212 R/W Address Base Address hex R/W Address Base Address hex Bit 2 Bit 1 EP10 EP9 R/W Address Base Address ...
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... ZL50212 ECA: Non-Linear Processor Threshold Power-up 0C ECB: Non-Linear Processor Threshold hex Bit 7 Bit 6 Bit 5 NLP15 NLP14 NLP13 ECA: Non-Linear Processor Threshold Power-up E0 ECB: Non-Linear Processor Threshold hex Bit 7 Bit 6 Bit 5 NLP7 NLP6 NLP5 This register allows the user to program the level of the Non-Linear Processor Threshold (NLPTHR). The 16 bit 2’ ...
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... ECA: Gains Register 2 ECB: Gains Register 2 Bit 4 Bit 3 Rin0 0 ECA: Gains Register 1 ECB: Gains Register 1 Bit 4 Bit 3 Sin0 0 Functional Description of Register Bits ) default hex Zarlink Semiconductor Inc. ZL50212 R/W Address Base Address hex R/W Address Base Address hex Bit 2 Bit 1 Bit 0 Rout2 Rout1 Rout0 R/W Address: ...
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... ZL50212 Power-up 00 Bit 7 Bit 6 WR_all ODE Write all control bit: When high, Group 0-15 Echo Cancellers Registers are mapped into 0000 WR_all to 0003F which is Group 0 address mapping. Useful to initialize the 16 Groups of Echo hex Cancellers as per Group 0. When low, address mapping is per Figure 10. Note: Only the Main Control Register 0 has the WR_all bit Output Data Enable: This control bit is logically AND’ ...
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... Bit 4 Bit 3 MTDBI MTDAI Functional Description of Register Bits , to the default Reset Value and clears the Adaptive Filter hex Zarlink Semiconductor Inc. ZL50212 R/W Address: 401hex R/W Address: 402hex R/W Address: 403hex R/W Address: 404hex R/W Address: 405hex R/W Address: 406hex R/W Address: 407hex R/W Address: 408hex R/W Address: 409hex ...
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... ZL50212 Power-up 00 Bit 7 Bit 6 IRQ 0 IRQ Logic high indicates an interrupt has occurred. IRQ bit is cleared after the Interrupt FIFO register is read. Logic Low indicates that no interrupt is pending and the FIFO is empty. 0 Unused bit. Always zero. 0 Unused bit. Always zero. I<4:0> I<4:0> binary code indicates the channel number at which a Tone Detector state change has occurred ...
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