zl50212 Zarlink Semiconductor, zl50212 Datasheet - Page 15

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zl50212

Manufacturer Part Number
zl50212
Description
288 Channel Voice Echo Canceller
Manufacturer
Zarlink Semiconductor
Datasheet
Data Sheet
Back-to-Back configuration is selected by writing a “1” into the BBM bit of Control Register 1 for both Echo Canceller
A and Echo Canceller B for a given group of echo canceller. Table 4 shows the 16 groups of 2 cancellers that can
be configured into Back-to-Back.
Examples of Back-to-Back configuration include positioning one group of echo cancellers between a codec and a
transmission device or between two codecs for echo control on analog trunks.
3.3
In this configuration, the two echo cancellers from the same group are internally cascaded into one 128 milliseconds
echo canceller. See Figure 8. This configuration uses only one timeslot on PORT1 and PORT2 and the second
timeslot normally associated with ECB contains quiet code.
Extended Delay configuration is selected by writing a “1” into the ExtDl bit in Echo Canceller A, Control Register 1.
For a given group, only Echo Canceller A, Control Register 1, has the ExtDl bit. For Echo Canceller B Control
Register 1, Bit 0 must always be set to zero.
Table 4 shows the 16 groups of 2 cancellers that can each be configured into 64ms or 128ms echo tail capacity.
Extended Delay configuration
Figure 8 - Extended Delay Configuration (128ms)
echo
path A
PORT2
Rout
Sin
channel A
channel A
ECA
Zarlink Semiconductor Inc.
Adaptive Filter
(128 ms)
-
+
PORT1
Sout
Rin
ZL50212
15

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