zl50051gag2 Zarlink Semiconductor, zl50051gag2 Datasheet - Page 56

• Manufacturer Part Number: zl50051gag2
• Description: 8 K Channel Digital Switch With High Jitter Tolerance, Single Rate 8 Or 16 Mbps And 64 Input And 64 Output Streams
• Manufacturer: Zarlink Semiconductor

Local and Backplane Data Timing
1
2
3
4
5
L/BSTo0-31
8.192 Mbps
8.192 Mbps
L/BSTi0-31
Note *: CK_int is the internal clock signal of 131.072 MHz
CK_int *
Local/Backplane Input Data Sampling Point
Local/Backplane Serial Input Set-up Time
Local/Backplane Serial Input Hold Time
Output Frame Boundary Offset
Local/Backplane Serial Output Delay
CK_int *
FP8o
FP8i
C8o
C8i
Ch127
Characteristic
Bit1
Figure 20 - ST-BUS Local/Backplane Data Timing Diagram (8 Mbps)
1
Ch127
Bit0
0
t
OFBOS
Ch0
Bit7
t
7
SOD8
t
t
SIS8
IDS8
t
SIH8
Zarlink Semiconductor Inc.
Ch0
ZL50051/3
Bit6
6
t
t
t
t
t
OFBOS
Sym.
t
SOD16
t
t
t
IDS16
SIS16
SIH16
SOD8
IDS8
SIH8
SIS8
56
Ch0
Bit5
5
Min.
43
87
2
2
2
2
Bit4
Ch0
4
Typ.
46
92
7
Ch0
Bit3
3
Max.
9.5
4.5
4.5
49
97
Ch0
Bit2
Units
2
ns
ns
ns
ns
ns
Ch0
Bit1
With
SMPL_MODE =
0 (3/4-bit
sampling) and
zero offset.
With respect to
Min. Input Data
Sampling Point
With respect to
Max. Input Data
Sampling Point
C
These numbers
are referencing
output frame
boundary.
1
L
= 50 pF
Data Sheet
Notes