zl50051gag2 Zarlink Semiconductor, zl50051gag2 Datasheet - Page 30

• Manufacturer Part Number: zl50051gag2
• Description: 8 K Channel Digital Switch With High Jitter Tolerance, Single Rate 8 Or 16 Mbps And 64 Input And 64 Output Streams
• Manufacturer: Zarlink Semiconductor

8.3
This feature allows fast, simultaneous, initialization of the Local and Backplane Connection Memories after
power-up. When the Memory Block Programming mode is enabled, the contents of the Block Programming
Register (BPR) will be loaded into the connection memories. See Table 13 and Table 14 for details of the Control
Register and Block Programming Register values, respectively.
8.3.1
•
•
The Backplane Block Programming data bits, BBPD[2:0], of the Block Programming Register, will be loaded into
bits[15:13] respectively, of the Backplane Connection Memory. The remaining bit positions are loaded with zeros as
shown in Table 6.
The Block Programming Register bit, BPE will be automatically reset LOW within 125 s, to indicate completion of
memory programming.
The Block Programming Mode can be terminated at any time prior to completion by clearing the BPE bit of the
Block Programming Register or the MBP bit of the Control Register.
Note that the default values (LOW) of LBPD[2:0] and BBPD[2:0] of the Block Programming Register, following a
device reset, can be used.
During reset, all output channels go HIGH or high impedance, depending on the value of the LORS and BORS
pins, irrespective of the values in bits[14:13] of the connection memory.
BBPD2
LBPD2
Set the MBP bit in the Control Register from LOW to HIGH.
Set the BPE bit to HIGH in the Block Programming Register (BPR). The Local Block Programming data bits,
LBPD[2:0], of the Block Programming Register, will be loaded into bits[15:13] of the Local Connection
Memory. The remaining bit positions are loaded with zeros as shown in Table 5.
15
15
Connection Memory Block Programming
Memory Block Programming Procedure:
BBPD1
LBPD1
Source Stream Bit Rate
14
14
Table 6 - Backplane Connection Memory in Block Programming Mode
Table 4 - Local and Backplane Connection Memory Configuration
Table 5 - Local Connection Memory in Block Programming Mode
16 Mbps
8 Mbps
LBPD0
BBPD0
13
13
12
0
12
0
11
0
11
0
Zarlink Semiconductor Inc.
Source Stream No.
legal values 0:31
legal values 0:15
10
ZL50051/3
0
10
0
Bits[12:8]
Bits[12:8]
9
0
30
9
0
8
0
8
0
7
0
7
0
6
0
6
0
Source Channel No.
legal values 0:127
legal values 0:255
5
0
5
0
Bits[7:0]
Bits[7:0]
4
0
4
0
3
0
3
0
2
0
2
0
Data Sheet
1
0
1
0
0
0
0
0