zl50051gag2 Zarlink Semiconductor, zl50051gag2 Datasheet - Page 11

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zl50051gag2

Manufacturer Part Number
zl50051gag2
Description
8 K Channel Digital Switch With High Jitter Tolerance, Single Rate 8 Or 16 Mbps And 64 Input And 64 Output Streams
Manufacturer
Zarlink Semiconductor
Datasheet
Pin Description (continued)
Backplane and Local Inputs
BSTi16-31
Pin Name
LSTi16-31
BSTi0-15
LSTi0-15
FP16o
72, 66, 65, 64
52, 46, 45, 44
Coordinates
256, 1, 2, 3,
83, 81, 82,
79, 80, 77,
78, 75, 76,
73, 74, 71,
63, 62, 61,
59, 60, 57,
58, 55, 56,
53, 54, 51,
228, 229,
230, 231,
232, 233,
234, 235,
236, 238,
237, 240,
239, 242,
248, 250,
249, 252,
251, 254,
253, 255,
ZL50053
Package
241, 244
4, 6, 5, 8
(256 pin
LQFP)
NA
T2, T3, T4, T5
Coordinates
M2, M3, M4,
N1, N2, N3,
N5, P1, P2,
R1, R2, R3,
R4, R5, T1,
K1, K2, K3,
L3, L4, M1,
P3, P4, P5,
K4, L1, L2,
M13, M14,
M15, M16,
N12, N13,
R12, R13,
R14, R15,
K13, K14,
K15, K16,
N16, P12,
P13, P14,
P15, P16,
R16, T12,
T13, T14,
L13, L14,
L15, L16,
N14, N15
ZL50051
Package
(256 ball
T15, T16
PBGA)
P11
N4
Zarlink Semiconductor Inc.
ZL50051/3
Frame Pulse Output (5 V Tolerant Three-state Output)
When the Frame Pulse Width bit (FPW) of the Control
Register is LOW (default), this pin outputs a 61 ns-wide frame
pulse. When the FPW bit is HIGH, this pin outputs a
122 ns-wide frame pulse. The frame pulse, running at 8 kHz
rate, will have the same format (ST-BUS or GCI-Bus) as the
input frame pulse (FP8i). Output data on both the Backplane
and Local sides (BSTo0-31 and LSTo0-31) will be aligned to
this frame pulse and the accompanying output clock, C16o.
Backplane Serial Input Streams 0 to 15 (5 V Tolerant Inputs with
Internal Pull-downs)
These pins accept serial TDM data streams at a data rate of:
16.384 Mbps (with 256 channels per stream), or 8.192 Mbps
(with 128 channels per stream).
Backplane Serial Input Streams 16 to 31 (5 V Tolerant Inputs with
Internal Pull-downs)
These pins accept serial TDM data streams at a data rate of:
8.192 Mbps (with 128 channels per stream).
When the device operates at 16.384 Mbps, these pins are
unused and should be externally connected to a defined logic
level.
Local Serial Input Streams 0 to 15 (5 V Tolerant Inputs with
Internal Pull-downs)
These pins accept serial TDM data streams at a data rate of:
16.384 Mbps (with 256 channels per stream), or 8.192 Mbps
(with 128 channels per stream).
Local Serial Input Streams 16 to 31 (5 V Tolerant Inputs with
Internal Pull-downs)
These pins accept serial TDM data streams at a data rate of:
8.192 Mbps (with 128 channels per stream).
When the device operates at 16.384 Mbps, these pins are
unused and should be externally connected to a defined logic
level.
11
Description
Data Sheet

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