zl50051gag2 Zarlink Semiconductor, zl50051gag2 Datasheet - Page 24

• Manufacturer Part Number: zl50051gag2
• Description: 8 K Channel Digital Switch With High Jitter Tolerance, Single Rate 8 Or 16 Mbps And 64 Input And 64 Output Streams
• Manufacturer: Zarlink Semiconductor

3.2
This feature is used to advance the output channel alignment of individual Local or Backplane output streams with
respect to the frame boundary FP8o. Each output stream has its own advancement value that can be programmed
by the Output Advancement Registers. The output advancement selection is useful in compensating for various
parasitic loading on the serial data output pins.
The Local and Backplane Output Advancement Registers, LOAR0 - LOAR31 and BOAR0 - BOAR31, are used to
control the Local and Backplane output advancement respectively. The advancement is determined with reference
to the internal system clock rate (131.072 MHz). The advancement can be 0, -2 cycles, -4 cycles or -6 cycles, which
converts to approximately 0 ns, -15 ns, -31 ns or -46 ns as shown in Figure 11.
Figure 10 - Backplane and Local Input Bit Delay or Sampling Point Selection Timing Diagram for
BID[4:0]/LID[4:0] = 00000
BID[4:0]/LID[4:0] = 00011
SMPL_MODE = HIGH
BID[4:0]/LID[4:0] = 00000
BID[4:0]/LID[4:0] = 00011
SMPL_MODE = LOW
Output Advancement Programming (Backplane and Local Output Streams)
Bit delay = 0 bit (Default)
Please refer to Control Register (Section 13.1) for SMPL_MODE definition.
3/4 sampling (Default)
Bit Delay = 3/4 bit
BSTi/LSTi0-31
BSTi/LSTi0-31
BSTi/LSTi0-31
BSTi/LSTi0-31
2/4 sampling
FP8i
FP8i
C8i
C8i
B
B
B
B
1
1
1
Ch127
Ch127
Ch127
Ch127
1
0
0
0
Zarlink Semiconductor Inc.
Data Rate of 8 Mbps
ZL50051/3
0
7
7
7
24
sample at 2/4 point
sample at 3/4 point
sample at 3/4 point
7
6
6
6
Ch0
Ch0
Ch0
sample at 3/4 point
Ch0
6
5
5
5
5
4
4
4
4
3
3
3
3
2
2
2
Data Sheet
2