zl50051gag2 Zarlink Semiconductor, zl50051gag2 Datasheet - Page 41

• Manufacturer Part Number: zl50051gag2
• Description: 8 K Channel Digital Switch With High Jitter Tolerance, Single Rate 8 Or 16 Mbps And 64 Input And 64 Output Streams
• Manufacturer: Zarlink Semiconductor

13.3
Addresses 0023
There are thirty-two Local Input Bit Delay Registers (LIDR0 to LIDR31).
When the SMPL_MODE bit in the Control Register is LOW, the input data sampling point defaults to the 3/4 bit
location and LIDR0 to LIDR31 define the input bit and fractional bit delay of each Local stream. The possible bit
delay adjustment is up to 7 3/4 bits, in steps of 1/4 bit.
When the SMPL_MODE bit is HIGH, LIDR0 to LIDR31 define the input bit sampling point as well as the integer bit
delay of each Local stream. The input bit sampling point can be adjusted in 1/4 bit increments. The bit delay can be
adjusted in 1-bit increments from 0 to 7 bits.
The LIDR0 to LIDR31 registers are configured as follows:
13.3.1
When SMPL_MODE = LOW, these five bits define the amount of input bit delay adjustment that the receiver uses to
sample each input. Input bit delay adjustment can range up to 7 3/4 bit periods forward, with resolution of 1/4 bit
period. The default sampling point is at the 3/4 bit location.
This can be described as: no. of bits delay = LID[4:0] / 4
For example, if LID[4:0] is set to 10011 (19), the input bit delay = 19 *
When SMPL_MODE = HIGH, the binary value of LID[1:0] refers to the input bit sampling point (1/4 to 4/4). LID[4:2]
refer to the integer bit delay value (0 to 7 bits). This means that bits can be delayed by an integer value of up to 7
and that the sampling point can vary from 1/4 to 4/4 in 1/4-bit increments.
(where n = 0 to 31)
Local Input Bit Delay Registers (LIDR0 to LIDR31)
Local Input Delay Bits 4-0 (LID[4:0])
LIDRn Bit
15:5
4:0
H
to 0042
H
.
Table 15 - Local Input Bit Delay Register (LIDRn) Bits
Reserved
LID[4:0]
Name
Reset
Value
Zarlink Semiconductor Inc.
0
0
ZL50051/3
Reserved
Must be set to 0 for normal operation
Local Input Bit Delay Register
When SMPL_MODE = LOW, the binary value of these
bits refers to the input bit and fractional bit delay value (0
to 7 3/4).
When SMPL_MODE = HIGH, the binary value of LID[1:0]
refers to the input bit sampling point (1/4 to 4/4). LID[4:2]
refer to the integer bit delay value (0 to 7 bits).
41
1
/
4
= 4
3
/
4
Description
.
Data Sheet