zl50051gag2 Zarlink Semiconductor, zl50051gag2 Datasheet - Page 14

• Manufacturer Part Number: zl50051gag2
• Description: 8 K Channel Digital Switch With High Jitter Tolerance, Single Rate 8 Or 16 Mbps And 64 Input And 64 Output Streams
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
JTAG Control Signals
Pin Name
RESET
TCK
TMS
R/W
DTA
TDo
TDi
CS
DS
Coordinates
ZL50053
Package
(256 pin
LQFP)
151
157
152
150
148
143
147
145
146
Coordinates
ZL50051
Package
(256 ball
PBGA)
C10
D10
B12
C11
C12
B11
A8
A6
A7
Zarlink Semiconductor Inc.
ZL50051/3
Chip Select (5 V Tolerant Input)
Active LOW input used by the microprocessor to enable the
microprocessor port access. Note that a minimum of 30 ns
must separate the de-assertion of DTA (to high) and the
assertion of CS and/or DS to initiate the next access.
Data Strobe (5 V Tolerant Input)
This active LOW input works in conjunction with CS to enable
the microprocessor port read and write operations. Note that
a minimum of 30 ns must separate the de-assertion of
DTA (to high) and the assertion of CS and/or DS to initiate
the next access.
Read/Write (5 V Tolerant Input)
This input controls the direction of the data bus lines (D0-D15)
during a microprocessor access.
Data Transfer Acknowledgment (5 V Tolerant Three-state
Output)
This active LOW output indicates that a data bus transfer is
complete. A pull-up resistor is required to hold a HIGH level.
Note that a minimum of 30 ns must separate the
de-assertion of DTA (to high) and the assertion of CS
and/or DS to initiate the next access.
Device Reset (5 V Tolerant Input with Internal Pull-up)
This input (active LOW) asynchronously applies reset and
synchronously releases reset to the device. In the reset state,
the outputs LSTo0-31 and BSTo0-31 are set to a HIGH or high
impedance state, depending on the state of the LORS and
BORS external control pins, respectively. The assertion of this
pin also clears the device registers and internal counters.
Refer to Section 7.3 on page 28 for the timing
requirements regarding this reset signal.
Test Clock (5 V Tolerant Input)
Provides the clock to the JTAG test logic.
Test Mode Select (5 V Tolerant Input with Internal Pull-up)
JTAG signal that controls the state transitions of the TAP
controller.
Test Serial Data In (5 V Tolerant Input with Internal Pull-up)
JTAG serial test instructions and data are shifted in on this pin.
Test Serial Data Out (5 V Tolerant Three-state Output)
JTAG serial data is output on this pin on the falling edge of
TCK. This pin is held in a high impedance state when JTAG is
not enabled.
14
Description
Data Sheet