mt9079apr1 Zarlink Semiconductor, mt9079apr1 Datasheet - Page 64

• Manufacturer Part Number: mt9079apr1
• Description: Advanced Controller For E1
• Manufacturer: Zarlink Semiconductor

AC Electrical Characteristics - Data Link Timing
Notes:
1. The falling edge of DLCLK occurs on the channel 0, bit 4 to bit 3 boundary of every second ST-BUS frame. The falling edge of IDCLK
occurs on the channel 16, bit 4 to bit 3 boundary of every second ST-BUS frame.
ST-BUS Bit
Stream
C2i
C4i
DLCLK
RxFDL
ST-BUS Bit
Stream
C2i
C4i
IDCLK*
TxFDL
* This clock signal is internal to the MT9079 and cannot be accessed by the user.
1
2
3
4
Data Link Clock Output Delay
Data Link Output Delay
Data Link Setup
Data Link Hold
Characteristic
Channel 0, Bit 4
Channel 16, Bit 4
Figure 21 - Transmit Data Link Timing Diagram
Figure 20 - Receive Data Link Timing Diagram
t
DLS
Sym.
t
t
t
t
Channel 0, Bit 3
Channel 16, Bit 3
Zarlink Semiconductor Inc.
t
DOD
DCD
DLS
DLH
DLH
t
t
DCD
DCD
MT9079
t
DOD
Min.
20
30
64
Typ.
Channel 0, Bit 2
Channel 16, Bit 2
Max.
75
75
Units
ns
ns
ns
ns
150 pF, See Note 1
150 pF
Conditions/Notes
V
V
V
V
TT
TT
TT,
TT
V
V
V
V
TT
TT
TT,
TT,
Data Sheet
V
CT
V
V
CT
CT