mt9079apr1 Zarlink Semiconductor, mt9079apr1 Datasheet - Page 22

• Manufacturer Part Number: mt9079apr1
• Description: Advanced Controller For E1
• Manufacturer: Zarlink Semiconductor

RAI and Continuous CRC-4 Error Counter
When the receive Remote Alarm Indication is active (RAI = 1 - bit 3 of the NFAS) and a receive E-bit indicates a
remote error (En = 0), the RCRC counter will be incremented. This counter will count the number of submultiframes
that were received in error at the remote end of a link during a time when layer one capabilities were lost at that
end. This eight bit RCRC counter is located on page 4, addresses 19H.
There are two maskable interrupts associated with the RCRC counter. RCRI is initiated when the least significant
bit of the RCRC counter toggles, and RCRO and EBO are initiated when the counter changes from FFH to 00H.
Maintenance and Alarms
Error Insertion
Five types of error conditions can be inserted into the transmit PCM 30 data stream through control bits, which are
located on page 2, address 10H. These error events include the bipolar violation errors (BPVE), CRC-4 errors
(CRCE), FAS errors (FASE), NFAS errors (NFSE), and a loss of signal condition (LOSE). The LOSE function
overrides the HDB3 encoding function.
Circular Buffers
The MT9079 is equipped with two 16 byte circular receive buffers and two 16 byte circular transmit buffers, which
can be connected to any PCM 30 time slot. Connection is made through control bits 3 to 0 of the per time slot
control words on pages 7 and 8. These buffers will transmit and receive time slot data synchronously with the CRC-
4 multiframe.
Transmit circular buffer zero is located on page 9 (TxB0.0 to TxB0.15) and transmit circular buffer one is located on
page 10 (TxB1.0 to TxB1.15).
The two circular 16 byte receive buffers (page 11 - RxB0.0 to RxB0.15 and page 12 - RxB1.0 to RxB1.15) record
the data received in an associated channel for the next 16 frames beginning with the CRC-4 multiframe boundary.
The assigned channel data from the next multiframe will over-write the current data until the buffer is disconnected.
The STOP and START maskable interrupts extend the normal operation of the receive buffers in the following
manner.
The functionality and control of the START and STOP interrupts is described in Table 6.
a. STOP - once activated, receive circular buffer 0 or 1 records time-slot data until that data either matches
b. START - once activated, receive circular buffer 0 or 1 begins recording time-slot data and initiates an
or mismatches a user-defined eight bit pattern, then the interrupt occurs. This user-defined bit pattern is
determined by the Code Detect Word (CDW) and Detect Word Mask (CDM) mentioned below.
interrupt when a user-defined eight bit pattern is received. This user-defined bit pattern is determined by
the Code Detect Word (CDW) and Detect Word Mask (CDM) mentioned below.
Zarlink Semiconductor Inc.
MT9079
22
Data Sheet