mt9079apr1 Zarlink Semiconductor, mt9079apr1 Datasheet - Page 15

• Manufacturer Part Number: mt9079apr1
• Description: Advanced Controller For E1
• Manufacturer: Zarlink Semiconductor

controlled frame slip. That is, the buffer pointers will be automatically adjusted so that a full PCM 30 frame is either
repeated or lost. All frame slips occur on PCM 30 frame boundaries.
The RSLIP and RSLPD status bits give indication of a slip occurrence and direction. A maskable interrupt SLPI is
also provided.
Figure 5 illustrates the relationship between the read and write pointers of the receive elastic buffer. Measuring
clockwise from the write pointer, if the read pointer comes within two channels of the write pointer a frame slip will
occur, which will put the read pointer 34 channels from the write pointer. Conversely, if the read pointer moves more
than 60 channels from the write pointer, a slip will occur, which will put the read pointer 28 channels from the write
pointer. This provides a worst case hysteresis of 13 channels peak (26 channels peak-to-peak) or a wander
tolerance of 208 UI.
When control bit RDLY=1, the receive elastic buffer becomes one frame long and the controlled slip function is
disabled. This is to allow the user to control the receive throughput delay of the MT9079 in one of the following
ways:
1. by programming the SOFF7-0 bits to select the desired throughput delay, which is indicated by the phase status
2. by controlling the position of the F0i pulse with respect to the received time slot zero position. The phase status
With RDLY=1, the elastic buffer may underflow or overflow. This is indicated by the RSLIP and RSLPD status bits.
If RSLPD=0, the elastic buffer has overflowed and a bit was lost; if RSLPD=1, a underflow condition occurred and a
bit was repeated.
Framing Algorithm
The MT9079 contains three distinct, but interdependent, framing algorithms. These algorithms are for basic frame
alignment, signalling multiframe alignment and CRC-4 multiframe alignment. Figure 6 is a state diagram that
illustrates these functions and how they interact.
After power-up the basic frame alignment framer will search for a frame alignment signal (FAS) in the PCM 30
receive bit stream. Once the FAS is detected, the corresponding bit two of the non-frame alignment signal (NFAS)
is checked. If bit two of the NFAS is zero a new search for basic frame alignment is initiated. If bit two of the NFAS
is one and the next FAS is correct, the algorithm declares that basic frame synchronization has been found (i.e.,
SYNC is low).
word bits RxTS4-0 and RxBC2-0.
word bits RxTS4-0 and RxBC2-0 will also indicate the delay in this application.
Read Pointer
47 CH
Read Pointer
60 CH
34 CH
512 Bit
Elastic
Store
Figure 5 - Elastic Buffer Functional Diagram (208 UI Wander Tolerance)
Write Pointer
28 CH
2 CH
Read Pointer
Read Pointer
15 CH
Zarlink Semiconductor Inc.
MT9079
-13 CH
15
13 CH
Wander Tolerance
Data Sheet