mt9079apr1 Zarlink Semiconductor, mt9079apr1 Datasheet - Page 54

• Manufacturer Part Number: mt9079apr1
• Description: Advanced Controller For E1
• Manufacturer: Zarlink Semiconductor

The TE control bit sets the state of the transmit E-bits when the receive side has lost CRC-4 synchronization. In
this case if the interface is the Terminal Equipment (TE) side, then the E-bits must be zero. If the interface is the
Network Termination (NT) side, the transmit E-bits must be one when CRC-4 synchronization is lost. When CRC-4
synchronization is achieved the transmit E-bits will function according to ITU-T G.704.
The MT9079 has a suite of 30 maskable interrupts. At this point in the initialization procedure the SYNI, RAII, AISI,
AIS16I, LOSI, FERI, BPVO and SLPI interrupts will be unmasked and all others will be masked. If the application
does not require interrupts, the SPND control bit should be kept at one.
Adjusting the ST-BUS offset will move the bit positions of the ST-BUS output streams with respect to the input
frame pulse F0i. This can be used to compensate for large delays in very long backplane applications. It can also
be used to minimize the delay through the receive elastic buffer.
Power-on Reset - RESET
supply rise time
input = RC > = 5 x power
Write 00H to all control
registers of pages 7 & 8
Select mode of operation.
Note 1.
Select National bit, data
link, and AIS mode of
operation. Note 1.
8KSEL bit = 1 if using the
E8Ko output for loop
(slave) timing. Note 1.
TAIS input = low
SPND bit = 1
START
A
Figure 12 - MT9079 Initialization Procedure
Read interrupt vector
register, page 4. Note 3.
Select PCM 30 line
encoding. Note 1.
Clear the error counters
of page 4. Note 2.
Select ST-BUS offset.
Note 1.
Mask and unmask
interrupts. Note 1.
Zarlink Semiconductor Inc.
TAIS input = high
SPND = 0.
Note 3.
Equipment?
Interface
Terminal
STOP
MT9079
A
Is
NO
54
YES
TE bit = 1
Notes:
1. Skip if default option is required.
2. Skip if counters are not used.
3. Skip if interrupts are not used.
Data Sheet