mt9079apr1 Zarlink Semiconductor, mt9079apr1 Datasheet - Page 38

• Manufacturer Part Number: mt9079apr1
• Description: Advanced Controller For E1
• Manufacturer: Zarlink Semiconductor

1 - 0
7 - 0
Bit
Bit
7
6
5
4
3
2
DWM7
DWM0
Name
TxCAS
(00H)
RPSIG
Name
SPND
RDLY
BFAS
(0)
(0)
(0)
(0)
(0)
-
---
---
Table 35 - Interrupt, Signalling and BERT Control Word
Detect Word Mask. If one, the corresponding bit position is considered in the comparison
between the receive code detect word (CDW) bits and the selected receive time slot bit
pattern. If zero, the corresponding bit is excluded from the comparison.
Receive Delay. If one, the receive elastic buffer will be one frame in length and con-
trolled frame slips will not occur. The RSLIP and RSLPD status bit will indicate a buffer
underflow or overflow. If zero, the two frame receive elastic buffer and controlled slip
functions are activated.
Suspend Interrupts. If one, the IRQ output will be in a high-impedance state and all inter-
rupts will be ignored. If zero, the IRQ output will function normally.
Unused.
Transmit Channel Associated Signalling. If zero, the transmit section of the device is in
CAS mode. If one, it is in common channel signalling mode.
Register Programmed Signalling. If one, the transmit CAS signalling will be controlled by
programming page 5. If zero, the transmit CAS signalling will be controlled through the
CSTi2 stream. This bit has no function in ST-BUS mode.
Bit Error Count on Frame Alignment Signal. If zero, individual errors in bits 2 to 8 of the
receive FAS will increment the Bit Error Rate Counter (BERC). If one, bit errors in the
comparison between receive circular buffer one and the bit error rate compare word will
be counted.
Unused.
Table 34 - Receive Code Detect Bit Mask
(Page 1, Address 1AH)
Zarlink Semiconductor Inc.
(Address 19H)
MT9079
38
Functional Description
Functional Description
Data Sheet