mt9079apr1 Zarlink Semiconductor, mt9079apr1 Datasheet - Page 46

• Manufacturer Part Number: mt9079apr1
• Description: Advanced Controller For E1
• Manufacturer: Zarlink Semiconductor

4 - 0
7 - 4
1 - 0
Bit
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
3
2
RNU4-8
RNFAB
Name
Name
RALM
CRCT
CALN
1SEC
2SEC
RIU1
400T
RMA1-4
EBT
Table 54 - Receive Non-frame Alignment Signal (Page 3, Address 13H)
Name
X2, X3
8T
Table 55 - Receive Multiframe Alignment Signal (Page 3, Address 14H)
---
X1
Y
Receive International Use 1. This bit is received on the PCM 30 2048 kbit/sec. link in bit
position one of the non-frame alignment signal. It is used for CRC-4 multiframe alignment
or international use.
Receive Non-frame Alignment Bit. This bit is received on the PCM 30 2048 kbit/sec. link in
bit position two of the non-frame alignment signal. This bit should be one in order to differ-
entiate between frame alignment frames and non-frame alignment frames.
Receive Alarm. This bit is received on the PCM 30 2048 kbit/sec. link in bit position three
of the non-frame alignment signal. It is used to indicate an alarm from the remote end of
the PCM 30 link (1 - alarm, 0 - normal).
Receive National Use Four to Eight. These bits are received on the PCM 30 2048 kbit/sec.
link in bit positions four to eight of the non-frame alignment signal.
One Second Timer Status. This bit changes state once every 0.5 seconds and is synchro-
nous with the 2SEC timer.
Two Second Timer Status. This bit changes state once every second and is synchronous
with the 1SEC timer.
CRC-4 Timer Status. This bit changes from one-to-zero at the start of the one second inter-
val in which CRC errors are accumulated. This bit stays high for 8 msec.
E-Bit Timer Status. This bit changes from one-to-zero at the start of the one second interval
in which E-bit errors are accumulated. This bit stays high for 8 msec.
400 msec. Timer Status. This bit changes state when the 400 msec. CRC-4 multiframe
alignment timer expires.
8 msec. Timer Status. This bit changes state when the 8 msec. CRC-4 multiframe align-
ment timer expires.
CRC-4 Alignment. When CRC-4 multiframe alignment has not been achieved this bit
changes state every 2 msec. When CRC-4 multiframe alignment has been achieved this
bit is synchronous with the receive CRC-4 multiframe signal.
Unused.
Receive Multiframe Alignment Bits One to Four. These bits are received on the PCM
30 2048 kbit/sec. link in bit positions one to four of time slot 16 of frame zero of every
multiframe. These bit should be 0000 for proper multiframe alignment.
Receive Spare Bit X1. This bit is received on the PCM 30 2048 kbit/sec. link in bit posi-
tion five of time slot 16 of frame zero of every multiframe.
Receive Y-bit Alarm. This bit is received on the PCM 30 2048 kbit/sec. link in bit posi-
tion six of time slot 16 of frame zero of every multiframe. It indicates loss of multiframe
alignment at the remote end (1 -loss of multiframe alignment; 0 - multiframe alignment
acquired).
Receive Spare Bits X2 and X3. These bits are received on the PCM 30 2048 kbit/sec.
link in bit positions seven and eight respectively, of time slot 16 of frame zero of every
multiframe.
Table 53 - Timer Status Word
(Page 3, Address 12H)
Zarlink Semiconductor Inc.
MT9079
46
Functional Description
Functional Description
Functional Description
Data Sheet