mt91l61asr1 Zarlink Semiconductor, mt91l61asr1 Datasheet - Page 22

• Manufacturer Part Number: mt91l61asr1
• Description: 3 V Multi-featured Phone Codec With Programmable U/a Law Companding
• Manufacturer: Zarlink Semiconductor

† AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25
* Note: TxINC, refer to Control Register 1, address 00h.
AC Characteristics
3.14 dB =1.067 V
1
2
3
4
5
6
7
8
9
Analog input equivalent to
overload decision
Absolute half-channel gain
M ± to Dout
Tolerance at all other transmit
filter settings
(1 to 7 dB)
Gain tracking vs. input level
ITU-T G.714 Method 2
Signal to total Distortion vs. input
level.
ITU-T G.714 Method 2
Transmit Idle Channel Noise
Gain relative to gain at 1020 Hz
<50 Hz
60 Hz
200 Hz
300 - 3000 Hz
3000-3300 Hz
3300 Hz
3400 Hz
4000 Hz
4600 Hz
>4600 Hz
Absolute Delay
Group Delay relative to D
Power Supply Rejection
f=1020 Hz
Characteristics
rms
for A-Law, at the Codec. (V
†
°
for A/D (Transmit) Path
C and are for design aid only: not guaranteed and not subject to production testing.
AX
Ref
= 0.4 V and V
PSSR
A
A
Sym.
G
G
D
G
G
N
N
D
D
Li3.17
Li3.14
AX1
AX2
QX
CX
DX
TX
PX
RX
AX
Zarlink Semiconductor Inc.
- 0 dBm0 = A
MT91L60/61
-0.25
Min.
14.7
-0.2
-0.3
-0.6
-1.6
-0.9
-0.9
-1.2
5.4
Bias
35
29
24
30
=1.5 volts.)
22
Lo3.17
Typ.
4.246
-70.5
15.3
±0.1
-0.2
-0.6
360
750
380
130
750
-45
-23
-41
4.4
6.0
13
50
- 3.17 dB = 1.027 V
‡
-12.5
Max.
15.9
+0.2
0.25
0.25
0.25
0.25
6.6
0.3
0.6
1.6
-69
-25
-30
0.0
-25
-25
16
dBrnC0
dBm0p
Units
Vp-p
Vp-p
ms
ms
ms
ms
ms
rms
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
for µ-Law and 0 dBm0 = A
at frequency of minimum
µ-Law
A-Law
Both at Codec
Transmit filter gain=0 dB
setting.
TxINC = 0*
TxINC = 1*
@1020 Hz
3 to -40 dBm0
-40 to -50 dBm0
-50 to -55 dBm0
0 to -30 dBm0
-40 dBm0
-45 dBm0
µ-Law
A-Law
delay
500-600 Hz
600 - 1000 Hz
1000 - 2600 Hz
2600 - 2800 Hz
±100 mV peak signal on
V
µ-law
DD
Test Conditions
Data Sheet
Lo3.14
-