mt91l61asr1 Zarlink Semiconductor, mt91l61asr1 Datasheet - Page 18

• Manufacturer Part Number: mt91l61asr1
• Description: 3 V Multi-featured Phone Codec With Programmable U/a Law Companding
• Manufacturer: Zarlink Semiconductor

Note: Bits marked "-" are reserved bits and should be written with logic "0"
Control Register 2
CEn
DEn
D8
A/µ
Smag/ITU-T
CSL
1
1
1
0
0
0
0
CEn
2
7
When high, data written into the C-Channel register (address 05h) is transmitted during channel 1 on DSTo. When low, the
channel 1 timeslot is tri-stated on DSTo. Channel 1 data received on DSTi is read via the C-Channel register (address 05h)
regardless of the state of CEn. This control bit has significance only for ST-BUS operation and is ignored for SSI operation.
When high, data written into the D-Channel Register (address 06h) is transmitted (2 bits/frame) during channel 0 on DSTo.
The remaining six bits of the D-Channel carry no information. When low, the channel 0 timeslot is completely tri-stated on
DSTo. Channel 0 data received on DSTi is read via the D-Channel register regardless of the state of DEN. This control bit has
significance only for ST-BUS mode and is ignored for SSI operation.
When high, D-channel operates at 8 kb/s. When low, D-channel operates at 16 kb/s (default).
When high, A-Law encoding/decoding is selected for the MT91L60/61. When low,
When high, sign-magnitude code assignment is selected for the Codec input/output. When low, ITU-T code assignment is
selected for the Codec input/output; true sign, inverted magnitude (
CSL
DEn
1
0
0
0
0
1
1
6
1
CSL
D8
1
0
1
0
1
0
1
5
0
A/µ
4
Bit Clock rate (kHz)
Zarlink Semiconductor Inc.
Smag/
ITU-T
1536
2048
4096
MT91L60/61
N/A
128
256
512
3
18
CSL
2
2
CSL
1
CLOCKin (kHz)
1
µ
4096
4096
4096
1536
2048
4096
-Law) or true sign, alternate digit inversion (A-Law).
512
CSL
ADDRESS = 04h WRITE/READ VERIFY
0
0
µ
-Law encoding/decoding is selected.
SSI (default)
ST-BUS
Mode
Power Reset Value
SSI
SSI
SSI
SSI
SSI
0000 0010
Data Sheet