mt91l61asr1 Zarlink Semiconductor, mt91l61asr1 Datasheet - Page 16

• Manufacturer Part Number: mt91l61asr1
• Description: 3 V Multi-featured Phone Codec With Programmable U/a Law Companding
• Manufacturer: Zarlink Semiconductor

Register Summary
Note: Bits marked "-" are reserved bits and should be written with logic "0"
Gain Control Register 1
Gain Control Register 2
RxINC: When high, the receive path nominal gain is set to 0 dB. When low, this gain is -6.0 dB.
TxINC: When high, the transmit path nominal gain is set to 15.3 dB. When low, this gain is 6.0 dB.
RxFG
Receive Gain
n
Setting (dB)
(default) 0
= Receive Filter Gain bit n
RxINC RxFG
-1
-2
-3
-4
-5
-6
-7
-
7
7
STG
n
Side-tone Gain
= Side-tone Gain bit n
(default) OFF
Setting (dB)
6
-
6
-9.96
-6.64
-3.32
3.32
6.64
9.96
RxFG
2
0
0
0
0
0
1
1
1
1
RxFG
2
5
5
-
1
RxFG
RxFG
0
0
1
1
0
0
1
1
1
4
4
-
STG
0
0
0
0
0
1
1
1
1
2
RxFG
Zarlink Semiconductor Inc.
TxINC
MT91L60/61
0
1
0
1
0
1
0
1
3
3
-
0
STG
TxFG
0
0
1
1
0
0
1
1
STG
16
1
TxFG
2
2
2
2
n
Transmit Gain
= Transmit Filter Gain bit n
Setting (dB)
TxFG
(default) 0
STG
STG
1
1
0
1
0
1
0
1
0
1
1
2
3
4
5
6
7
0
1
1
TxFG
STG
ADDRESS = 00h WRITE/READ VERIFY
ADDRESS = 01h WRITE/READ VERIFY
0
0
0
0
TxFG
0
0
0
0
1
1
1
1
2
TxFG
Power Reset Value
Power Reset Value
0
0
1
1
0
0
1
1
XXXX X000
1000 0000
1
Data Sheet
TxFG
0
1
0
1
0
1
0
1
0