mt91l61asr1 Zarlink Semiconductor, mt91l61asr1 Datasheet - Page 12

• Manufacturer Part Number: mt91l61asr1
• Description: 3 V Multi-featured Phone Codec With Programmable U/a Law Companding
• Manufacturer: Zarlink Semiconductor

SSI Mode
The SSI BUS consists of input and output serial data streams named Din and Dout respectively, a Clock input
signal (CLOCKin), and a framing strobe input (STB). The frame strobe must be synchronous with, and eight cycles
of, the bit clock. A 4.096 MHz master clock is also required for SSI operation if the bit clock is less than 512 kHz.
The timing requirements for SSI are shown in Figures 12 & 13.
In SSI mode the MT91L60/61 supports only B-Channel operation. The internal C and D Channel registers used in
ST-BUS mode are not functional for SSI operation. The control bits TxBSel and RxBSel, as described in the ST-
BUS section, are ignored since the B-Channel timeslot is defined by the input STB strobe. Hence, in SSI mode
transmit and receive B-Channel data are always in the channel defined by the STB input.
The data strobe input STB determines the 8-bit timeslot used by the device for both transmit and receive data. This
is an active high signal with an 8 kHz repetition rate. The MT91L61 provides a delayed strobe pulse which occurs
after the initial strobe goes low and is held high for the duration of 8 pcm bits.
SSI operation is separated into two categories based upon the data rate of the available bit clock. If the bit clock is
512 kHz or greater then it is used directly by the internal MT91L60/61 functions allowing synchronous operation. If
the available bit clock is 128 kHz or 256 kHz, then a 4096 kHz master clock is required to derive clocks for the
internal MT91L60/61 functions.
Applications where Bit Clock (BCL) is below 512 kHz are designated as asynchronous. The MT91L60/61 will re-
align its internal clocks to allow operation when the external master and bit clocks are asynchronous. Control bits
CSL2, CSL1 and CSL0 in Control Register 2 (address 04h) are used to program the bit rates.
For synchronous operation data is sampled, from Din, on the falling edge of BCL during the time slot defined by the
STB input. Data is made available, on Dout, on the rising edge of BCL during the time slot defined by the STB input.
Dout is tri-stated at all times when STB is not true. If STB is valid and PDDR is set, then quiet code will be
transmitted on Dout during the valid strobe period. There is no frame delay through the FDI circuit for synchronous
operation.
For asynchronous operation Dout and Din are as defined for synchronous operation except that the allowed output
jitter on Dout is larger. This is due to the resynchronization circuitry activity and will not affect operation since the bit
cell period at 128 kb/s and 256 kb/s is relatively large. There is a one frame delay through the FDI circuit for
asynchronous operation. Refer to the specifications of Figures 12 & 13 for both synchronous and asynchronous
SSI timing.
Di-bit Group
Receive
D-Channel
IRQ
FP
D0
n-7
I
No preset value
D1
n-6
II
D2
III
n-5
D3
IV
n-4
Figure 7c - D-Channel 8 kb/s Operation
D4
n-3
V
D5
VI
n-2
Di-bit Group
D-Channel
Zarlink Semiconductor Inc.
D6
VII
Transmit
n-1
MT91L60/61
VIII
D7
n
12
D0
n+1
I
Power-up reset to 1111 1111
D1
n+2
II
Microport Read/Write Access
D2
III
n+3
D3
IV
n+4
D4
n+5
V
D5
VI
n+6
D6
VII
n+7
VIII
D7
n+8
D-Channel
Data Sheet