ml87v21071 Oki Semiconductor, ml87v21071 Datasheet - Page 71

• Manufacturer Part Number: ml87v21071
• Description: Video Signal Noise Reduction Ic With A Built-in Frame Memory
• Manufacturer: Oki Semiconductor

OKI Semiconductor
• Setting internal reflect timing
* Settings by I
Input System:
As mentioned above, it is possible to read/write data at successive sub-addresses starting from a certain
sub-address (continuous read/write). Read/write to a non-contiguous sub-address is performed by repeating
the acknowledge and stop conditions of input format (single read/write) of the above-mentioned data 0.
The IC does not return acknowledge in the following cases:
The input timing diagram is shown below.
reflect timing. If the setting is performed at a position that contains the above timing, the setting may not finish
inside the same field.
Slave-address does not match.
Non-existing sub-address is specified.
SDA
SCL
Start Condition
Slave Address W
Slave Address R
Sub Address
Data Line Stable: Data Valid
Symbol
2
Data n
S
C-bus interface should be made by avoiding the position of above-mentioned setting internal
A(m)
A(s)
Sr
S
P
IVS fall position (IVSINV = 0) or IVS rise position (IVSINV = 1).
MSB
1
Table F4 (2) Description of the I
Figure F4 I
Start condition
Restart condition
Slave address 1011_1XX0 (XX is set externally.)
Slave address 1011_1XX1 (XX is set externally.)
Acknowledge (Slave side generates.)
Acknowledge (Master side generates.)
Sub-address byte
Data byte
Stop condition
2
3-6
Change of Data Allowed
2
C-bus Interface Basic Timing
7
8
ACK
9
Description
2
C-bus Format
1
2
3-8
ACK
9
Stop Condition
PEDL87V21071-01
P
ML87V21071
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