ml87v21071 Oki Semiconductor, ml87v21071 Datasheet - Page 66

• Manufacturer Part Number: ml87v21071
• Description: Video Signal Noise Reduction Ic With A Built-in Frame Memory
• Manufacturer: Oki Semiconductor

3.3 Output Signal Level Range Settings
3.4 CLKO Output Setting
OKI Semiconductor
ITU-R601 compliance is specified for the input signal level range for this IC. Output is normally the same as
input, but where 00h and FFh are input for the valid data period, you can set the output signal level range to be 01h
to FEh by setting the I
As a data latch for post-stage ICs of this IC, the CLKO pin can output a clock synchronized with data. Enable
control of the CLKO pin is possible with CKEN (SUB:60h-bit[7]).
In normal mode, ICLK is output. When TEST7 is set to 1, IICLK (same as 16-bit mode: ICLK; 8-bit or ITU-R
BT.656 mode:1 /2 division of ICLK) or ICLK can be selected in CKSL (SUB:60h-bit[6]).
Further, by setting CKINV (SUB:60h-bit[5]) as necessary, the polarity of the CLKO output clock can be inverted.
2
* In the 16-bit input mode, IICLK = ICLK.
C-bussettings register R601(SUB:40h-bit[6]) = 1.
[CKINV=0]
[CKINV=1]
Figure F3-4 (1) CLKO Output Timing (16-Bit Mode)
CLKO
CLKO
ICLK
CKEN
0
1
1
1
1
Table F3-3 Output Signal Level Range
CKSL
R601
Table F3-4 CLKO Output
X
0
0
1
1
0
1
CKINV
Output signal level
X
0
1
0
1
00h to FFh
01h to FEh
t
CKD
range
IICLK inversion
ICLK inversion
CLKO output
IICLK
ICLK
Hi-Z
PEDL87V21071-01
ML87V21071
66/123