ml87v21071 Oki Semiconductor, ml87v21071 Datasheet - Page 20

• Manufacturer Part Number: ml87v21071
• Description: Video Signal Noise Reduction Ic With A Built-in Frame Memory
• Manufacturer: Oki Semiconductor

1.1.5 Input System Detection Field Inversion Setting
1.1.6 Input System Vertical Reset Compensation Mode Setting
OKI Semiconductor
Condition
Inversion of input system internal field detection is possible by setting IFINV (SUB:42h-bit[2]) by I
interface. However, setting is not necessary if there is no problem in normal detection.
* PAL
* NTSC
In this IC, the rear edge (in the case of standard signal, 625 lines; A-3 line, 0.5H position, in between B-315 and
B-316 lines, 525 lines; A-6 line, 0.5H position, in between B-6 and B-7 lines) of normally standard vertical Sync.
signal (IVS) is regarded as the reference position (IVR generating position) to perform field detection and
memory control.
If a Sync. signal with unspecified phase of the IVS rear edge and horizontal Sync. signal (IHS) is input, the front
edge can be used with the setting IVSINV = 1. But if the front edge is used in standard 626-line mode, the
detection filed reverses in normal operation and field B gets written in the memory with one line earlier phase.
Therefore, by setting the I
B→A) and the vertical phase with regard to field B of the inverted result is delayed by 1H.
This allows compensation for field detection and IVR which is the typical front edge phase of IVS of 625-line
mode.
In practice, this allows compliance with the Sync. signal examples shown in Table F1-1-6 and Figure F1-1-6.
Note: Use it in case the phase of field-detecting IVS and IHS reverses in the IC standard setting.
Phase 1
Phase 2
Phase 3
Phase 4
Table F1-1-6 Input System Vertical Reset Compensation by IVEM Setting
IVSINV = 0
IVSINV = 0
IVSINV = 1
IVSINV = 1
Front edge
Front edge
Rear edge
Rear edge
reference
:
:
Vertical
Field A = 1st, 3rd, 5th, 7th color field
Field B = 2nd, 4th, 6th, 8th color field
Field A = 2nd, 4th color field
Field B = 1st, 3rd color field
2
C-bus setting register IVEM (SUB:42h-bit[4]), the detection field is inverted (A→B,
data field
IFINV
Input
A
B
A
B
A
B
A
B
0
1
Table F1-1-5 IFIND Setting
decision field
Internal
A
B
B
A
A
B
B
A
Field A
0
1
Input field
setting
IVEM
0
1
0
1
Field B
1
0
No compensation
No compensation
compensation
Field after
A
B
A
B
PEDL87V21071-01
Valid data start
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position
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2
C-bus