ml87v21071 Oki Semiconductor, ml87v21071 Datasheet
ml87v21071
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ml87v21071 Summary of contents
Page 1
... Video Signal Noise Reduction IC with a Built-in Frame Memory GENERAL DESCRIPTION The ML87V21071, which comprises a frame memory and signal processing and memory control logic circuits, has achieved motion-adaptive 3D noise reduction. To perform noise reduction with afterimage suppression, the ML87V21071 also enables noise reduction using the edge-adaptive 2D noise reduction filter ...
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... OKI Semiconductor BLOCK DIAGRAM Input/Output Process Block 3D NR YI0-7 x16 CI0 ICLK IVS IHS SCL 2 I C-bus SDA SLA1 I/F SLA2 Register MODE0-4 TEST0-5 RESET Frame x16 Memory + + + Memory Controller Control Signal PEDL87V21071-01 ML87V21071 x16 YO0-7 CO0-7 OVS OHS HREF CLKO 2/123 ...
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... OE 82 N.C. 83 N.C. 84 N.C. 85 N.C. 86 TEST5 TEST4 89 TEST3 90 TEST2 91 TEST1 92 TEST0 93 N.C. 94 N.C. 95 TESTM 96 TSELF N. 100 DD ML87V21071TB (TQFP100-P-1414-0.5-K) PEDL87V21071-01 ML87V21071 N. HREF 47 OVS 46 OHS 45 N.C. 44 N.C. 43 N. N.C. N. CLKO 35 MODE2 34 N.C. 33 MODE1 32 ...
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... Input system vertical Sync. signal input pin Input system horizontal Sync. signal input pin Mode setting pin bit 0 (Equivalent to internal register VMD[0]) Mode setting pin bit 1 (Equivalent to internal register HMD[0]) Unused pin PEDL87V21071-01 ML87V21071 Termination of unused pin Not used Not used or ...
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... Luminance signal output pin bit 7 (MSB) Ground Test input pin bit 7 (1: Test mode) Test input pin bit 6 (1: Test mode) System reset/input pin 0: System reset 1: Operation 3.3 V power supply PEDL87V21071-01 ML87V21071 Termination of unused pin Not used or connected to GND Not used X X Not used ...
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... Test input pin bit 0 (1: test mode) Unused pin Unused pin Memory test input pin (1: test mode) Self refresh test input setting pin Ground Unused pin 3.3 V power supply PEDL87V21071-01 ML87V21071 Termination of unused pin Not used X Not used or connected to GND Not used or connected to GND ...
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... Typ. V 3.0 3 — Symbol Min. C — — — o PEDL87V21071-01 ML87V21071 Rating Unit –0 0.5 ≤ 4.6 –0 ° °C –50 to +150 Max. Unit 3 ° 3.3 V ± 0 MHz 25°C) Max ...
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... CKD (ICLK output DIDO / 0 reaches 3.0 V after the power is turned on. (Due to memory initialization, DD PEDL87V21071-01 ML87V21071 ( 70°C) Min. Max. Unit × 0 × 0.3 –0 × 0. × 0.25 –0 × ...
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... DATA & CONTROL INPUT (ICLK) DATA & CONTROL OUTPUT (ICLK) CLKO (CKINV=0) CLKO (CKINV=1) 2. Data through Mode Input/Output Timing DATA & CONTROL INPUT DATA & CONTROL OUTPUT t ICLK t t IISU IIH t IOD t CKD t CKD t DIDO PEDL87V21071-01 ML87V21071 50% 50% 50% 50% 50% 50% 50% 9/123 ...
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... RESET pin for more to initialize the internal circuits. * After the RESET pin goes to 1, the I 1ms (Min.) Don't care (3.0 to 3.6 V) from 0 V after power is turned on, input 0 to the DD 2 C-bus interface can be used while the input of ICLK is stable. PEDL87V21071-01 ML87V21071 10/123 ...
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... Input/Output 1.1 Memory Control The ML87V21071 accesses data to the input data frame memory by generating a line access type memory control signal from Sync. signals of the IVS and IHS pin inputs or the Sync. signals separated from SAV and EAV, and achieves noise reduction of frame/field/line adaptation recursive type. ...
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... Standard clock Number of Standard pixels frequency f ICLK valid lines [MHz] 288 27 243 27 288 29.5 243 24.545454 288 29.5 243 28.63636 Test modes is as follows: IICLK PEDL87V21071-01 ML87V21071 Valid pixels per line 864 720 858 720 944 768 780 640 944 768 910 768 12/123 ...
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... A input, the pulse toggled by IVS is regarded as the field pulse. IVS IHS 0.5H pulse #IF Figure F1-1-2 (1) Input System Field A Detection Timing IVS IHS 0.5H pulse #IF Figure F1-1-2 (2) Input System Field B Detection Timing PEDL87V21071-01 ML87V21071 Field A detection phase Field A detection phase Field B detection phase Field B detection phase 13/123 ...
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... Figure F1-1-2 (3) Field Detection during Continuous Same Field Input (FCON = 1) Field A judgment area IHS or 0.5H pulse Field judgment margin (10 clocks) Field judgment uncertainty area Figure F1-1-2 (4) Field Judgment Uncertainty Area PEDL87V21071-01 Field A Field A Field B Field A Field B judgment area Field judgment margin (10 clocks) Field judgment uncertainty area ML87V21071 14/123 ...
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... Test modes (not settable) HMD Valid lines [0] [1] [ 576(572 486(482 576(572 486(482 576(572 486(482) Test modes (not settable) PEDL87V21071-01 ML87V21071 Valid pixels 720 720 768 640 768 768 Valid pixels 720 720 768 640 768 768 15/123 ...
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... OKI Semiconductor IHS IWE IRE YI CI Figure F1-1-3(1) Input Vertical Valid Lines IHS IWE IRE YI CI Figure F1-1-3(2) Input Horizontal Valid Pixels 243/288/486/576lines : Valid data : Invalid data 720/640/768pixels : Valid data : Invalid data PEDL87V21071-01 ML87V21071 16/123 ...
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... NPVWE=10h …… 49 (default) …… 27 (default) 7 lines 7 lines IVPS 15 lines 15 lines IVPS 576/486 lines PEDL87V21071-01 ML87V21071 …… NPVWE=Fh …… 27 (+7 lines) …… 21 (+7 lines) …… 31 (+7 lines) (*1) …… 26 (+7 lines) (*1) …… NPVWE=1Fh …… ...
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... Test modes (Setting inhibited) 127 pixels IHPS 640/720/768 pixels 1 pixel Valid data PEDL87V21071-01 ML87V21071 …… NHPWE=FFh …… 271 (+127 pixels) …… 265 (+127 pixels) …… 303 (+127 pixels) …… 267 (+127 pixels) … ...
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... IWE Value set by NPVWE[3:0] 2 C-bus setting register IHSINV (SUB:42h-bit[1]). Table F1-1-4 (2) IHSINV Setting IHSINV Input IHS polarity 0 Positive (default) 1 Negative IHSINV=1 IHS IWE Value set by NPHWE[7:0] PEDL87V21071-01 ML87V21071 IVR generation edge Rising edge Falling edge Value set by NPVWE[3:0] Value set by NPHWE[7:0] 19/123 ...
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... Field Internal IVEM decision field setting PEDL87V21071-01 ML87V21071 2 C-bus Field Field after Valid data start compensation position n No compensation compensation 20/123 ...
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... Input sync signal phase 3 Field A input IHS IVS n-1 n #IVR #IF Field B input IHS IVS n-1 n #IVR #IF Input sync signal phase 4 Field A input IHS IVS n-1 n #IVR #IF Field B input IHS IVS n-1 n n+1 0 #IVR #IF PEDL87V21071-01 ML87V21071 n-1 n n+1 ...
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... STLM [ Input data writing Possible (field A restoration) Possible (field B restoration) Possible (either field restoration) Stopped (field A maintained) Stopped (field B maintained) Stopped (either field output maintained) Output still image [0] X Field image 0 Frame image 1 Frame image (median) PEDL87V21071-01 ML87V21071 22/123 ...
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... Writing stop processing start position Frame for pre-stop Stopping period write processing Writing stop processing start position Valid data Valid data Valid data PEDL87V21071-01 ML87V21071 Writing restoration set Stopping period Writing stop processing end position ...
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... Cr04 — — Cr03 — — Cr02 — — Cr01 — — Cr00 — — PEDL87V21071-01 ML87V21071 2 C-bus setting register IRMON Mode Cr07 Y17 Cr06 Y16 Cr05 Y15 Cr04 Y14 Cr03 Y13 Cr02 Y12 Cr01 Y11 Cr00 Y10 — ...
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... Figure F1-2-1 (1) Input Data Timing IVS IHS YI[7:0], CI[7:0] (YCbCr-4:2:2) = 12.2727272/13.5/14.31818/14.75 MHz ICLK None IVS IHS YI[7:0], (YCbCr-4:2:2) = 24.545454/27/28.63636/29.5 MHz ICLK None SAV, EAV split SAV, EAV split YI[7:0] (YCbCr-4:2: MHz ICLK 00h → 01h, FFh → Feh PEDL87V21071-01 ML87V21071 Cbn Yn Crn Yn+1 don't care (no connect) 25/123 ...
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... Positive polarity IHS rise (horizontal Sync. signal front edge) Positive polarity IHS fall (horizontal Sync. signal rear edge) Negative polarity IHS fall (horizontal Sync. signal front edge) Negative polarity IHS rise (horizontal Sync. signal rear edge) Usage conditions (8-bit 4:2:2 mode) Crn PEDL87V21071-01 ML87V21071 Yn Cbn Yn+1 26/123 ...
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... Sync (H, V) 16-bit + Sync (H, V) 8-bit + Sync (H, V) 8-bit + Sync (H, V) 8-bit + Sync (H, V) 8-bit + Sync (H, V) ITU-R BT.656 16-bit + Sync (H, V) ITU-R BT.656 ITU-R BT.656 + Sync (H, V) PEDL87V21071-01 ML87V21071 Cb07 Y17 Cb06 Y16 Cb05 Y15 Cb04 Y14 Cb03 Y13 ...
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... FF 00 [DOSEL=0] YO[7:0] CO[7:0] [DOSEL=1] YO[7:0] Figure F1-2-2(3) Input/Output Delay in ITU-R BT.656 Mode Y0 Y1 Cb0 Cr0 32(ICLK) Cb0 Y0 Cr0 Y1 64(ICLK) 66(ICLK) 00 SAV Cb0 Y0 Cr0 Y1 64(ICLK 66(ICLK) PEDL87V21071-01 ML87V21071 Cb0 Cr0 Cb1 Cb0 Cr0 Cb0 Cb0 Y0 Cr0 Y1 SAV Cb0 Cr0 Cb0 ...
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... Non- Limiter compen- linear filter sation MSB Motion detection Chrominance noise detection Chrominance Non- motion level Limiter compen- linear filter sation Motion detection PEDL87V21071-01 ML87V21071 + Luminance - output data - Field memory NR recursive data + Chrominance - output data - Luminance interlock motion Field compensation memory ...
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... OKI Semiconductor Current field data – – One preceding field data Figure F2-1(2) Noise Reduction by Noise Detection – – Noise detection + motion compensation PEDL87V21071-01 ML87V21071 Data after 3DNR 30/123 ...
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... NR for edges) This IC detects motions and edges between lines, frames, and fields, based on the features described above, to select data after better correlated NR and achieve effective noise reduction. Figure F2-1 (3) Noise Reduction Correlation Time axis 2V Direction NR-target pixel : NR PEDL87V21071-01 ML87V21071 1H 31/123 ...
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... NR (uses frames and fields) 2D adaptive frame-recursive NR (uses frames and lines) Frame-recursive NR 2D adaptive field-recursive NR (uses fields and lines) Field-recursive NR margin 0 Frame NR performance emphasized (larger –2 NR, larger afterimage) Margin 0 Frame NR performance emphasized (larger –2 NR, larger afterimage) PEDL87V21071-01 ML87V21071 Remarks Remarks 32/123 ...
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... Noise detection line Input noise detection line inclination 1 or 7/8 or 3/4 or 1/2 Non-noise detection area Noise convergence line inclination -1 or -3/4 or -1/2 or -3/2 Noise upper limit line Noise detection area PEDL87V21071-01 ML87V21071 Noise upper limit line Inclination Offset YLM[4:0] 0 CLM[4:0] Noise upper limit line offset: ...
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... Table F2-1-3 (2) Luminance 3 Continuous Code Motion Detection Motion detection condition - (1/8)z + (1/2)z + (1/8)z + (1/8)z Motion Flag (YMT) | ∆ LY| > ∆ LY| > YNS[5:0] | ∆ LY| ≤ YNS[5:0] Motion flag (YMT3) | ∆ LY| > ∆ LY| ≥ YMS[3:0] | ∆ LY| < YMS[3:0] PEDL87V21071-01 ML87V21071 34/123 ...
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... Motion flag (YMT4) | ∆ LY| > ∆ LY| ≥ YMS[3:1] | ∆ LY| < YMS[3:1] Motion flag (YMT5) | ∆ LY| > ∆ LY| ≥ YMS[3:2] | ∆ LY| < YMS[3: (1/2)z + (1/4)z Motion flag (CMT) | ∆ LC| > ∆ LC| > CNS[5:0] | ∆ LC| ≤ CNS[5:0] PEDL87V21071-01 ML87V21071 35/123 ...
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... Luminance 4 continuous codes chrominance motion compensation Luminance 5 continuous codes chrominance motion compensation Motion compensation Remarks mode None Detected noise as is (Detected noise) x Normal reduction (Reduction coefficient) (Detected noise) x Absolute noise reduction (Reduction coefficient) Noise 0 judgment Noise 0 (NROFF) PEDL87V21071-01 ML87V21071 Remarks 36/123 ...
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... PEDL87V21071-01 ML87V21071 YABN = 1 1 3/4 3/4 5/8 5/8 9/16 9/16 17/32 Remarks Detected noise as is (Detected noise) x (Reduction coefficient) (Detected noise) x (Reduction coefficient) Noise 0 judgment (NROFF) CABN=1 1 3/4 3/4 5/8 3/4 5/8 5/8 9/16 5/8 9/16 9/16 17/32 9/16 17/32 17/32 1/2 37/123 ...
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... Table F2-1-6 NRDEMO Setting Left side of screen [ setting value X Stop NR 1 Stop Setting value 0 NR Setting value PEDL87V21071-01 ML87V21071 2 C-bus interface. Right side of screen NR setting value Stop NR NR setting value Adaptive NR ON Adaptive line correlation NR ON Right side area of screen 38/123 ...
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... By setting YNMAS (SUB:57-bit[0]) and CNMAS (SUB:57h-bit[1]), it is possible to select either an 8-frame average of the detected noise (YNMAS = 0, CNAMS = 0) or the level of detected noise in a single frame (YNMAS = 1, CNAMS = 1). For a noise detection area, a vertical blanking period, a valid data period combination of both can be set using PODT (SUB:49h-bit[4]) and PNON (SUB:49h-bit[7]). PEDL87V21071-01 ML87V21071 39/123 ...
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... Internal signal Figure F2-1-7 (1) Vertical Blanking Noise Status Detection timing (NDTC = 0) #Valid data signal IHS NRDTP[3:0] (DTPSL=0) NRDTP[3:0] (DTPSL=1) #: Internal signal Figure F2-1-7 (2) Vertical Blanking Noise Status Detection timing (NDTC = NDTP[3:0]+1 NDTP[3:0]+1 PEDL87V21071-01 ML87V21071 40/123 ...
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... OKI Semiconductor 128pixels Figure F2-1-7(3) Noise Level Detection Area 128pixels 128pixels 128pixels 128pixels 128pixels PEDL87V21071-01 ML87V21071 Vertical blanking period horizontal valid data noize level detection period (2 x 128 pixels) Vertical blanking noise level detection period ( lines) Vertical valid line noise level detection period ...
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... NRDTP[3:0] YNAMS Noise detection value CNAMS 0 Average of 8 frames 1 Single frame PNON Noise detection area 0 Vertical blanking only Vertical blanking only + valid data period X Valid data period only Luminance saturation level No saturation level E0h C0h 80h PEDL87V21071-01 ML87V21071 Field A Field B 42/123 ...
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... YAH1 Noise reduction direction CAH1 switching coefficient 0 3/4 1 7/8 Noise reduction direction judging threshold value Noise increase direction judging threshold value 0 YAVR1[6:0] CAVR1[6:0] PEDL87V21071-01 ML87V21071 After transition YBDTO After transition CBDTO Basic average noise value YBAVRO[6:0] CBAVRO[6:0] ...
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... Blanking period ≤ Valid data period Blanking period > Valid data period — PEDL87V21071-01 ML87V21071 Luminance judgment noise level Blanking period noise level Valid data period noise level Blanking period noise level Valid data period noise level Valid data period noise level ...
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... YAVRO[6:0] ≤ YAVR2[6:0] YAVRO[6:0] > YAVR2[6:0] YAVRO[6:0] ≤ YAVR2[6:0] x (hysteresis coefficient) YAVRO[6:0] > YAVR2[6:0] x (hysteresis coefficient) Condition CAVRO[6:0] ≤ CAVR2[6:0] CAVRO[6:0] > CAVR2[6:0] CAVRO[6:0] ≤ CAVR2[6:0] x (hysteresis coefficient) CAVRO[6:0] > CAVR2[6:0] x (hysteresis coefficient) PEDL87V21071-01 ML87V21071 After transition YDTO1 After transition CDTO1 After transition ...
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... Luminance detection mask detection Noise reduction direction judging threshold value 1 Noise increase direction judging threshold value 1 Noise reduction direction judging threshold value 2 Noise increase direction judging threshold value 2 Set by YAH2, CAH2 YAVR1[6:0] YAVR2[6:0] CAVR1[6:0] CAVR2[6:0] PEDL87V21071-01 ML87V21071 Average noise value YAVRO[6:0] CAVRO[6:0] 46/123 ...
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... Luminance judgment noise status 2 (noise medium/high judgment) Chrominance judgment maximum noise value Chrominance judgment noise status 2 (noise medium/high judgment) Luminance blanking average noise value Luminance blanking noise status (basic noise judgment) Luminance blanking average noise value Luminance blanking noise status (basic noise judgment) PEDL87V21071-01 ML87V21071 47/123 ...
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... AMM (SUB:49h-bit[3]). The noise reduction setting value in auto mode can be precisely set by AYABN (SUB:4Ah-bit[3]), ACABN (SUB:4Bh-bit[3]), AYNS[1:0] (SUB:4Eh-bit[7:6]), ACLM[1:0] (SUB:4Fh-bit[7:6]), AYMS [1:0] (SUB:50h-bit[7:6]), and AYMOFF[3:1] (SUB:51h-bit[7:5]). (SUB:4Ch-bit[7:6]), ACNS[1:0] PEDL87V21071-01 ML87V21071 (SUB:4Dh-bit[7:6]), AYLM [1:0] 48/123 ...
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... Valid data period Fixed value noise follow-up noise reduction noise reduction (with lower limit) PEDL87V21071-01 ML87V21071 Remarks Same as NROFF = 1 AYNS [1:0], YCNA [1:0], AYLM [1:0], YCLM [1:0], and AYMS [1:0] are valid. YNRM, CNRM, YABN and CABN settings are ignored; operation is equivalent to YNRM = 1, CNRM = 1, YABN = 0, CABN = 0, and YMDM = 1 ...
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... Valid data period Fixed value noise follow-up noise reduction noise reduction (with lower limit) PEDL87V21071-01 ML87V21071 Remarks AYNS [1:0], YCNA [1:0], AYLM [1:0], YCLM [1:0], and AYMS [1:0] are valid. YNRM, CNRM, YABN and CABN settings are ignored; operation is equivalent to YNRM = 1, CNRM = 1, YABN = 0, CABN = 0, and YMDM = 1. ...
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... Absolute noise reduction mode (equivalent to 1 CABN = 1 operation) AYNS Luminance noise convergence level [1] [ YNS[5:0] + YMAXO[4:0](max:3Fh Smaller of YMAXO[4:0] x 3(max:3Fh) and YNS[5: YNS[5:0] + YMAXO[4:0](max:3Fh Larger of YMAXO[4:0] x 3(max:3Fh) and YNS[5:0] PEDL87V21071-01 ML87V21071 YNS[5:0] YNS[5:0] YNS[5:0] 51/123 ...
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... Chrominance noise upper limit level [1] [ Smaller of CMAXO[4:0] x 0.75 (max:1Fh) and CLM[4: Smaller of CMAXO[4:0](max:1Fh) and CLM[4: Larger of CMAXO[4:0] x 0.75(max:1Fh) and CLM[4: Larger of CMAXO[4:0](max:1Fh) and CLM[4:0] PEDL87V21071-01 ML87V21071 CNS[5:0] CNS[5:0] CNS[5:0] YLM[4:0] YLM[4:0] YLM[4:0] CLM[4:0] CLM[4:0] CLM[4:0] 52/123 ...
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... Motion compensation YMOFF[a] X dependent Motion compensation YMOFF[a] 0 dependent Motion compensation stopped (equivalent 1 to YMOFF[ Luminance motion compensation Motion compensation YMOFF[a] X dependent Motion compensation YMOFF[a] 0 dependent Motion compensation stopped (equivalent 1 to YMOFF[ Luminance adaptive margin setting YFAM dependent Equivalent to YFAM = 1 operation PEDL87V21071-01 ML87V21071 53/123 ...
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... CDTO1 is 1, the line correlation NR is set to be OFF. Table F2-1-8 (14) Line Correlation NR OFF Settings Blanking period noise Chrominance adaptive margin setting CFAM dependent Equivalent to CFAM = 1 operation YDTO1 or Line correlation NR setting CDTO1 X NR2OFF dependent 0 NR2OFF dependent 1 Line correlation NR OFF PEDL87V21071-01 ML87V21071 54/123 ...
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... Noise state detection is not performed at all times if the hysteresis characteristic of noise state detection is not valid (frequent occurrence of state switching). The noise detection is performed by NRDTON = 1 (8 frames or more) at the time of RF channels or input source switching only. Thereafter, settings to hold the noise state etc., at NRDTON = the next switching become necessary. PEDL87V21071-01 ML87V21071 55/123 ...
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... While the cross-color cancellation function is active, chrominance recursive type noise reduction does not function. • When using the cross-color cancellation function, set MEM411 to “1” and the internal memory to the 4:1:1 use mode since two-frame chrominance data needs to be used. PEDL87V21071-01 ML87V21071 56/123 ...
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... When using the movement compensation function, be sure to set MEM411 (SUB:5Eh-bit[1 and the memory use mode to 4:1:1. Before cross-color cancellation Figure F2-2-1 Cross-Color Cancellation in the NTSC System PEDL87V21071-01 ML87V21071 2 C-bus interface, the 3D comb filter After cross-color cancellation 57/123 ...
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... Table F2-2-3 Cross-Color Cancellation Auto-OFF Setting ACC [1] [ After cross-color cancellation 2 C-bus interface, the cross-color cancellation can be stopped Cross-color cancellation Set by CCON Goes OFF if YDT1 = 1 when CCON = 1 Goes OFF if YDT2 = 1 when CCON = 1 PEDL87V21071-01 ML87V21071 58/123 ...
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... C-bus interface, only chrominance signals can be displayed by fixing 2 C-bus interface, the cross-color cancellation function can be checked CCT Luminance signal 0 Input luminance signal 1 80h fixed Left side on the screen Right side on the screen CC setting value CC setting value CCOFF CC setting value PEDL87V21071-01 ML87V21071 Right-side area on the screen 59/123 ...
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... YED[4:0] (SUB:65h-bit[4:0]). When the difference V_average V_average PEDL87V21071-01 ML87V21071 0 ) and : Target pixel to be averaged : Edge detection : Not used when 3 pixels are averaged YH 13 60/123 ...
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... H_filter Figure F2-3-2 Chrominance Edge-Adaptive 2D Noise Reduction 0 +2 +(1/8 +(1/4 PEDL87V21071-01 ML87V21071 0 ) and : Filtering-target pixel : Edge detection CH 13 61/123 ...
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... C-bus interface, the edge-adaptive 2D noise reduction Table F2-3-4 ODEMO Setting Left side of screen Right side of screen YLPFON, CLPFON setting YLPFON, CLPFON setting Edge-adaptive 2D OFF YLPFON, CLPFON setting Normal edge-adaptive 2D YLPFON, CLPFON setting PEDL87V21071-01 ML87V21071 2 C-bus interface, the 2D NR OFF OFF ON ON OFF OFF ON ...
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... This IC has a luminance edge correction function that reduces the luminance band deterioration after 2D decoding in the input system. 2.4.1 Luminance Edge Correction When YECON (SUB:64h-bit[5]) is set to 1, luminance data edge correction operates. Undershoot or overshoot does not occur as a result of edge correction. Table F2-4-1 Luminance Edge Correction Setting YECON Luminance edge correction 0 OFF 1 ON PEDL87V21071-01 ML87V21071 63/123 ...
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... Horizontal reference signal Chrominance select signal Output system filed pulse signal l-1 l l+1 l+2 l+3 3 pixels Y_BLK (00, 01, 08, 10 C_BLK (80) Cb0 Cr0 Cb1 Cr1 Horizontal valid data period PEDL87V21071-01 ML87V21071 m pixels Y3 Ym-3 Ym-2 Ym-1 Ym Y_BLK (00,01,08,10) Cbn-1 Crn-1 Cbn Crn C_BLK (80 BLK 64/123 ...
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... OVSINV OVS output 0 Input same polarity 1 Input opposite polarity Table F3-2(2) OVS Pin Polarity OHSINV OHS output 0 Input same polarity 1 Input opposite polarity Table F3-2(3) HREF Pin Polarity HREF output 0 Internally generated same polarity 1 Internally generated opposite polarity PEDL87V21071-01 ML87V21071 Blanking Period 65/123 ...
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... CLKO [CKINV=1] CLKO Figure F3-4 (1) CLKO Output Timing (16-Bit Mode) R601 Output signal level range 0 00h to FFh 1 01h to FEh Table F3-4 CLKO Output CKSL CKINV CLKO output IICLK 0 1 IICLK inversion 1 0 ICLK 1 1 ICLK inversion t CKD PEDL87V21071-01 ML87V21071 66/123 ...
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... OKI Semiconductor ICLK #IICLK [CKSL=0,CKINV=0] CLKO [CKSL=0,CKINV=1] CLKO [CKSL=1,CKINV=0] CLKO [CKSL=1,CKINV=1] CLKO Figure F3-4 (2) CLKO Output Timing (8-Bit/ITU-R BT.656 Mode in Input) t CKD PEDL87V21071-01 ML87V21071 67/123 ...
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... Table F3-5 Input Through Mode Input pin Output pin YI[7:0] YO[7:0] CI[7:0] CO[7:0] IVS OVS OHS IHS HREF Internal Circuit PASS = 0: Internal processing signal output PASS = 1: Signal through PASS Figure F3-5 Input Through Mode PEDL87V21071-01 ML87V21071 Y YO[7:0] CO[7: OVS OHS Y Y HREF 68/123 ...
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... C interface is reflected in the IC internal section synchronously with IVS. 2 C-bus setting register RLTG (SUB:72h-bit[7]) can release RLTG Data reflection 0 Synchronized with IVS 2 1 When set PEDL87V21071-01 ML87V21071 Output pins other than data Enable Enable Enable Enable Disable Disable Enable the 69/123 ...
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... C-bus interface standards of Philips. This allows setting a Table F4 (1) Slave Address Slave Address (Write) Slave Address (Read) 0 B8h 1 BAh 0 BCh 1 BEh A(s) Data 0 A(s) Data n A(s) A(s) Data 0 P A(s) Sr Slave Address R A(s) A(s) Sr Slave Address R A(s) PEDL87V21071-01 ML87V21071 B9h BBh BDh BFh A/A(s) P A(m) Data 0 A(m) Data n P A(m) Data 0 P 70/123 ...
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... If the setting is performed at a position that contains the above timing, the setting may not finish inside the same field. 2 C-bus Format Description 3-6 ACK Change of Data Allowed 2 C-bus Interface Basic Timing PEDL87V21071-01 ML87V21071 9 3-8 P ACK Stop Condition 71/123 ...
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... The subaddress registers 40h to 7Fh of this IC are set to the initial values of the register map as a result of input of system reset (RESET pin = 0). For the reserved registers that are not included in the register map, 00h data is set as the initial value. Note: Blank (reserved) registers must be set to 0. PEDL87V21071-01 ML87V21071 72/123 ...
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... CMOFF YAVR1 CAVR1 YAVR2 CAVR2 NRDTP YAVRO PEDL87V21071-01 ML87V21071 Initial Sync value BIT1 BIT0 VMD 00h IVS 1 0 R656I DISEL 00h — IHSINV IVSINV 00h IVS STL 00h IVS 1 0 08h IVS 1 0 80h ...
Page 74
... TST TST AROS — OEINV RYNS RCNS RYLM RCLM PEDL87V21071-01 ML87V21071 Initial Sync value BIT1 BIT0 IVS 00h ( IVS 00h ( IVS 00h ( IVS 00h 1 0 (R) IVS 00h ( CCON ...
Page 75
... SHSDL TST PEDL87V21071-01 ML87V21071 Initial Sync value BIT0 IVS 00h (R) 0 ISYNC 00h — 00h — 0 00h — 55h (R) 0 AAh (R) 1 FFh (R) 1 21h (R) 1 71h ...
Page 76
... Vertical line operation mode setting [0] 0 625-line mode 1 525-line mode 0 Test mode 1 720-pixel mode Square (768/640) pixel mode 768-pixel mode Test mode PEDL87V21071-01 ML87V21071 BIT2 BIT1 BIT0 HMD VMD Sampling frequency 13.5 MHz 14.75/12.272727 MHz 14.75/14.31818 MHz — 76/123 ...
Page 77
... Sets external pin/internal registers switching for memory control mode setting Table R2-1 (5) External Pin Setting Switching Setting IRMON 0 1 Internal registers (VMD[0], HMD[0], DISEL, R656I, DOSEL) Input signal level range 00h to FFh ITU-R BT.601 (01h to FEh) Register set mode setting External pin (MODE[4:0]) PEDL87V21071-01 ML87V21071 77/123 ...
Page 78
... ICINV (Reserved) APN656 DISEL R656I Automatic 625/525 setting 0 OFF (VMD[0] setting) ON (automatic setting ITU-R BT.656 input mode only PEDL87V21071-01 ML87V21071 BIT2 BIT1 BIT0 R6561 DISEL Input data format 16-bit 4:2:2 YCbCr 8-bit 4:2:2 YCbCr ITU-R BT.656 mode 78/123 ...
Page 79
... Timing reference code during horizontal blanking period disabled. ICINV IICLK polarity 0 At IHS rise reset IHS rise reset: 0 IHES IHS edge for H reset 0 Rise 1 Fall POFF Parity check OFF Timing reference code detection All timing reference code enabled. PEDL87V21071-01 ML87V21071 79/123 ...
Page 80
... Negative polarity (Fall) IFINV Detection field pulse 0 Decision result 1 Decision result inversion IFLS Detection field pulse 0 IHS decision 1 0.5H pulse decision PEDL87V21071-01 ML87V21071 BIT2 BIT1 BIT0 IFINV IHSINV IVSINV IVS input polarity 2 Positive polarity (Rise) IHS input polarity 2 Positive polarity (Fall) 80/123 ...
Page 81
... Sets successive same field input countermeasure. Automatically generates both fields by detecting 8 or more successive same fields. Table R2-2-2 (6) Detection Field Pulse Polarity Setting FCON 0 1 IVS reset compensation No compensation Detection field pulse Decision result mode Automatic field generation mode PEDL87V21071-01 ML87V21071 81/123 ...
Page 82
... Possible (arbitrary field recovery Stop (field A data hold Stop (field B data hold Stop (arbitrary field data hold) Output mode [0] 0 Field output mode 1 Frame output mode (normal) 1 Frame output mode (median) PEDL87V21071-01 ML87V21071 BIT3 BIT2 BIT1 BIT0 STL 82/123 ...
Page 83
... When IHSINV = 1, sets the number of pixels from the IHS fall position. BIT6 BIT5 BIT4 4 BIT6 BIT5 BIT4 NPHWE INPR Input 0 Interlace (525i/625i) 1 Progressive input (525p/625p) PEDL87V21071-01 ML87V21071 BIT3 BIT2 BIT1 BIT0 NPVWE BIT3 BIT2 BIT1 BIT0 83/123 ...
Page 84
... NR setting value X Stop NR. 1 Stop NR. 0 Stop motion compensation. 0 Stop auto mode. Stop motion compensation. 0 Stop auto mode. PEDL87V21071-01 ML87V21071 BIT2 BIT1 BIT0 NRDEMO NROFF 1 0 Right side screen NR setting value Stop NR. NR setting value NR setting value NR setting value NR setting value ...
Page 85
... NR2OFF FNRM[1:0] Initial value:0; Setting range Sets the noise reduction recursive mode. Table R2-3-1 (3) Recursive Mode Settings FNRM [1] [ line correlation noise reduction 0 ON (adaptive) 1 OFF Mode Frame / field adaptive mode Frame mode Field mode PEDL87V21071-01 ML87V21071 85/123 ...
Page 86
... BIT6 BIT5 BIT4 BIT3 NDTC NRDTF PODT AMM Noise reduction mode Register fixed mode Auto mode Noise detection Stop (Hold) Updated every frame Chrominance noise detection flag mode Chrominance independent Luminance linked PEDL87V21071-01 ML87V21071 BIT2 BIT1 BIT0 ACY NRDTON NRAUTO 86/123 ...
Page 87
... PNON Noise detection period 0 Vertical blanking period only 1 Vertical blanking period + valid data period X Valid data period only PEDL87V21071-01 ML87V21071 YDTO1 = 1, YDTO2 = 1 CDTO1 = 1, CDTO2 = 1 Noise follow-up state (With automatic motion compensation OFF) Noise follow-up state (With automatic motion compensation OFF) 87/123 ...
Page 88
... CSLT[3:0] Initial value: 0001; Setting range: Refer to Table R2-3-3 (10). Sets chrominance noise reduction noise detection line/convergence line inclination. BIT5 BIT4 BIT3 YSLT AYABN BIT5 BIT4 BIT3 CSLT ACABN PEDL87V21071-01 ML87V21071 BIT2 BIT1 BIT0 YABN YFAM YNRM BIT2 BIT1 BIT0 CABN CFAM CNRM 88/123 ...
Page 89
... Noise follow-up state luminance mode Normal noise mode Absolute noise mode Noise follow-up state chrominance mode Normal noise mode Absolute noise mode PEDL87V21071-01 ML87V21071 89/123 ...
Page 90
... X – X – Noise detection line Noise convergence line coefficient (Inclination) [ 7/8 0 3/4 1 1/2 X – X – X – X – PEDL87V21071-01 ML87V21071 coefficient (Inclination) – – – – 1 (–1) 3/4 (–3/4) 1/2 (–1/2) 3/2 (–3/2) coefficient (Inclination) – – – – 1 (–1) 3/4 (–3/4) 1/2 (–1/2) 3/2 (–3/2) 90/123 ...
Page 91
... Figure R2-3-4 Example of Noise Detection by the YNS and CNS Settings BIT6 BIT5 BIT4 BIT3 BIT6 BIT5 BIT4 BIT3 Non-noise detection region Noise detection region YNS[5:0],CNS[5:0]= PEDL87V21071-01 ML87V21071 BIT2 BIT1 BIT0 YNS BIT2 BIT1 BIT0 CNS (Difference between the fields) Input 63 (MAX) 91/123 ...
Page 92
... Setting (Valid at NRAUTO=1) ACNS [1] [ Noise Follow-up State Noise Convergence Level YNS[5:0] YNS[5:0] + YMAXO[5:0] (Max.: 3Fh) YMAXO[5:0] × 3 (Max.: 3Fh) Noise Follow-up State Noise Convergence Level CNS[5:0] CNS[5:9] + CMAXO[5:0] (Max.: 3Fh) CMAXO[5:0] × 4 (Max.: 3Fh) PEDL87V21071-01 ML87V21071 92/123 ...
Page 93
... Sets auto mode chrominance noise upper limit level. Becomes valid in the auto mode noise follow-up state. BIT6 BIT5 BIT4 BIT3 AYNDL BIT6 BIT5 BIT4 BIT3 ACNDL PEDL87V21071-01 ML87V21071 BIT2 BIT1 BIT0 YLM BIT2 BIT1 BIT0 CLM 93/123 ...
Page 94
... Noise detection region Auto Mode Luminance Noise Upper Limit Level Noise Follow-up State Luminance Noise Upper Limit Level YLM[4:0] YMAXO[5:0] × 0.75 (Max.: 1Fh) YMAXO[5:0] (Max.: 1Fh) CLM[4:0] CMAXO[5:0] × 0.75 (Max.: 1Fh) CMAXO[5:0] (Max.: 1Fh) PEDL87V21071-01 ML87V21071 YLM[4:0], CLM[4: (Detected noise A) Input 94/123 ...
Page 95
... Small (No compensation) Motion decision Large (Compensation operation) Large (Compensation operation) Small (No compensation) Motion decision Large (Compensation operation) Large (Compensation operation) Small (No compensation) Noise follow-up state motion compensation level YMS[4:0] YMAXO[5:0] (Max.: Fh) YMAXO[5:0]/2 (Max.: Fh) PEDL87V21071-01 ML87V21071 BIT2 BIT1 BIT0 YMS 95/123 ...
Page 96
... Sets the auto mode line correlation noise reduction OFF. If there is a lot of noise in the auto mode, the line correlation noise reduction is turned OFF. Table R2-3-6 (5) Auto Mode Line Correlation Noise Reduction OFF Setting A2OFF 0 1 Line correlation noise reduction Depends on NR2OFF setting Line correlation OFF in noise status 2 PEDL87V21071-01 ML87V21071 96/123 ...
Page 97
... Luminance motion level detection noise motion compensation YMDM Detection setting 0 Detection setting weak 1 Detection setting strong Noise follow-up state motion compensation Motion compensation ON Motion compensation OFF PEDL87V21071-01 ML87V21071 BIT3 BIT2 BIT1 BIT0 YMOFF BIT3 BIT2 BIT1 BIT0 CMOFF ...
Page 98
... Luminance horizontal contiguous 4-continuous code motion compensation - ON Luminance horizontal contiguous 4-continuous code motion compensation - OFF Luminance horizontal contiguous 5-continuous code motion compensation - OFF Luminance horizontal contiguous 5-continuous code motion compensation - ON Luminance horizontal contiguous 5-continuous code motion compensation - OFF PEDL87V21071-01 ML87V21071 98/123 ...
Page 99
... Sets a noise detection luminance saturation level of the valid data area. Sets a level that does not perform noise judgment in noise detection in a valid data area. Table R2-3-7(6) Setting of a Noise Detection Luminance Saturation Level of Valid Data Area PYST[1: Luminance saturation level No saturation level E0h C0h 80h PEDL87V21071-01 ML87V21071 99/123 ...
Page 100
... BIT6 BIT5 BIT4 (Reserved BIT6 BIT5 BIT4 (Reserved BIT6 BIT5 BIT4 YAVR2 BIT6 BIT5 BIT4 CAVR2 PEDL87V21071-01 ML87V21071 BIT3 BIT2 BIT1 BIT0 YAVR1 BIT3 BIT2 BIT1 BIT0 CAVR1 BIT3 BIT2 BIT1 BIT0 ...
Page 101
... Level condition Level condition Level condition Level condition Noise decrease direction switching coefficient 3/4 7/8 Noise decrease direction switching coefficient 3/4 7/8 PEDL87V21071-01 ML87V21071 State YDTO1 = 0 → 1 YDTO1 = 1 → 0 State CDTO1 = 0 → 1 CDTO1 = 1 → 0 State YDTO2 = 0 → 1 YDTO2 = 1 → 0 State CDTO2 = 0 → 1 CDTO2 = 1 → 0 ...
Page 102
... Noise decrease direction switching coefficient 3/4 7/8 Noise decrease direction decision threshold value 1 Noise increase direction decision threshold value 1 Noise decrease direction decision threshold value 2 Noise increase direction decision threshold value 2 Set by YAH2, CAH2. YAVR1[6:0] YAVR2[6:0] CAVR1[6:0] CAVR2[6:0] PEDL87V21071-01 ML87V21071 Noise average value YAVRO[6:0] CAVRO[6:0] 102/123 ...
Page 103
... CAVRO [6:0], CMAXO[5: frames average 1 1 frame detection Noise detection reference position 0 1st line after valid data end line 1 2nd line after valid data end line PEDL87V21071-01 ML87V21071 BIT2 BIT1 BIT0 CNAMS YNAMS 1 0 103/123 ...
Page 104
... BIT6 BIT5 BIT4 BIT3 BIT6 BIT5 BIT4 BIT3 YBAVRO BIT6 BIT5 BIT4 BIT3 CBAVRO PEDL87V21071-01 ML87V21071 BIT2 BIT1 BIT0 BIT2 BIT1 BIT0 BIT2 BIT1 BIT0 YMAXO BIT2 BIT1 BIT0 CMAXO BIT2 ...
Page 105
... YBDTO Read value range Luminance base noise detection flag. At NRDTON = 1, YBDTO is set to “1” if YBAVRO[6:0] > YAVR1[5:0] state continues in 4 frames. CBDTO Read value range Chrominance base noise detection flag. At NRDTON = 1, CBDTO is set to “1” if CBAVRO[6:0] > CAVR1[5:0] state continues in 4 frames. PEDL87V21071-01 ML87V21071 105/123 ...
Page 106
... Same format for input and output HREF pin output [0] 0 Horizontal reference signal 1 Chrominance select signal 0 Effective area signal 1 Field pulse signal CKSL CKINV CLKO output IICLK inverted ICLK inverted PEDL87V21071-01 ML87V21071 BIT2 BIT1 BIT0 (Reserved) DOSEL (Reserved) Hi-Z IICLK ICLK 106/123 ...
Page 107
... HREFINV BIT6 BIT5 BIT4 (Reserved) (Reserved) (Reserved) (Reserved) Table-R2-4-2(1) OVS Polarity Setting OVS Polarity 0 Positive 1 Negative Table-R2-4-2(2) OHS Polarity Setting OHS Polarity 0 Positive 1 Negative HREF polarity 0 Positive polarity 1 Negative polarity PEDL87V21071-01 ML87V21071 BIT3 BIT2 BIT1 BIT0 HREF OHSINV OVSINV INV 107/123 ...
Page 108
... CCMDT BIT5 BIT4 BIT3 CCYMS CCMDT CCMON MEM411 1 0 BIT5 BIT4 BIT3 ACC Cross-color cancellation 0 OFF 1 ON Memory Format 0 4:2:2 1 4:1:1 Movement compensation 0 OFF 1 ON Movement detection 0 Weak 1 Strong PEDL87V21071-01 ML87V21071 BIT2 BIT1 BIT0 CCON BIT2 BIT1 BIT0 YCCNL 108/123 ...
Page 109
... Cross-color cancellation auto ON/OFF setting [0] 0 Cross-color cancellation auto ON/OFF disabled 1 If YDTO1 = 1, cross-color cancellation OFF 1 If YDTO2 = 1, cross-color cancellation OFF Test mode 0 Normal mode 1 Test mode (luminance is fixed to 80h) Demonstration mode 0 Normal mode 1 Demonstration mode (Left: OFF, Right: ON) PEDL87V21071-01 ML87V21071 109/123 ...
Page 110
... ON Luminance edge-adaptive 2D noise reduction 0 Filter weak 1 Filter strong Luminance edge-adaptive 2D noise reduction 0 3-pixel filter 1 5-pixel filter Chrominance edge-adaptive 2D noise reduction 0 OFF 1 ON PEDL87V21071-01 ML87V21071 BIT2 BIT1 BIT0 YHLPFM YLPFM YLPFON BIT2 BIT1 BIT0 YED BIT2 BIT1 BIT0 CED ...
Page 111
... Luminance edge adaptation level auto setting ON/OFF setting OFF (YED[4:0]) ON (if YDTO2 = 1, noise level is set) Luminance edge-adaptive 2D noise reduction auto ON/OFF setting [1] Stop luminance 2D noise reduction auto 0 ON/OFF. 1 Noise reduction ON when YDTO1 = 1. 0 Noise reduction ON when YDTO2 = 1. PEDL87V21071-01 ML87V21071 setting value value value 111/123 ...
Page 112
... Chrominance edge-adaptive 2D noise reduction auto ON/OFF [2] [ Chrominance edge adaptive level auto ON/OFF setting OFF (CED[4:0]) ON (if CDTO2 = 1, noise level is set) setting Chrominance edge-adaptive 2D noise reduction auto ON/OFF disabled Chrominance 2D noise reduction ON when CDTO1 = 1 Chrominance 2D noise reduction ON when CDTO2 = 1 PEDL87V21071-01 ML87V21071 112/123 ...
Page 113
... PAOS (Reserved) PASS Mode 0 Normal operation 1 Data through All output pins Dependent on other settings (OE, INT) Disable OE input pin Output data disable Output data disable Offset No offset 2H (INPR = 0)/4H (INPR = 1) PEDL87V21071-01 ML87V21071 BIT2 BIT1 BIT0 OEINV OUTDS PASS 113/123 ...
Page 114
... OKI Semiconductor RLTG Initial value: 0; Setting range Sets the register setting synchronous mode. Normally 0; used only for tests. Table R2-6-1 (5) Register Set Mode Setting RLTG 0 1 Data reflection Synchronized to IVS and OVS 2 When I C-bus is set PEDL87V21071-01 ML87V21071 114/123 ...
Page 115
... Sets test mode: Normally fixed to 0000_0000. BIT6 BIT5 BIT4 BIT3 TST BIT6 BIT5 BIT4 BIT3 TST BIT6 BIT5 BIT4 BIT3 TST PEDL87V21071-01 ML87V21071 BIT2 BIT1 BIT0 BIT2 BIT1 BIT0 BIT2 BIT1 BIT0 115/123 ...
Page 116
... Since this is a setting for demonstration, normally set this bit to 0. BIT5 BIT4 BIT3 BIT5 BIT4 BIT3 SHSDL ISYNC OVS, OHS output 0 Input (IVS, IHS)-delay output 1 Internally generated output OHS phase 0 Horizontal Sync. signal 1 Composite Sync PEDL87V21071-01 ML87V21071 BIT2 BIT1 BIT0 HSSEL ISYNC BIT2 BIT1 BIT0 116/123 ...
Page 117
... RYNR RYNRM OFF 4 3 BIT6 BIT5 BIT4 BIT3 RCNR RCNRM OFF 4 3 BIT6 BIT5 BIT4 BIT3 RYMOF RNR2 OFF PEDL87V21071-01 ML87V21071 BIT2 BIT1 BIT0 RYNS BIT2 BIT1 BIT0 RCNS BIT2 BIT1 BIT0 RYLM BIT2 BIT1 BIT0 RCLM ...
Page 118
... Reads luminance edge-adaptive 2D noise reduction ON/OFF switching signal of an internal operation status. RCLPF Read value range Reads chrominance edge-adaptive 2D noise reduction ON/OFF switching signal of an internal operation status. RCCON Read value range Reads cross-color cancellation ON/OFF switching signal of an internal operation status. PEDL87V21071-01 ML87V21071 118/123 ...
Page 119
... CI4 CO4 21 ML87V21071 56 CI3 CO3 22 54 CI2 CO2 23 53 CI1 CO1 24 52 CI0 CO0 IVS OVS 29 46 IHS OHS ICLK 16 PEDL87V21071-01 ML87V21071 YO7 YO6 YO5 YO4 YO3 YO2 YO1 YO0 SCAN DATA CONVERTER OUT HREF CLKO CLK 119/123 ...
Page 120
... CO5(OPEN) CI4(OPEN) 21 ML87V21071 56 CO4(OPEN) CI3(OPEN CO3(OPEN) CI2(OPEN CO2(OPEN) CI1(OPEN CO1(OPEN) CI0(OPEN CO0(OPEN) 47 HREF(OPEN) IVS(OPEN OVS(OPEN) IHS(OPEN OHS(OPEN) 35 CLKO(OPEN) ICLK(27MHz) 16 PEDL87V21071-01 ML87V21071 YO7 YO6 YO5 YO4 YO3 YO2 YO1 YO0 MPEG DATA ENCODER OUT CLK 120/123 ...
Page 121
... The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). PEDL87V21071-01 ML87V21071 (Unit: mm) Package material Epoxy resin ...
Page 122
... OKI Semiconductor REVISION HISTORY Document Date No. PEDL87V21071-01 Nov. 15, 2005 Page Previous Current Edition Edition – – Preliminary edition 1 PEDL87V21071-01 ML87V21071 Description 122/123 ...
Page 123
... The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these part of the contents contained herein may be reprinted or reproduced without our prior permission. PEDL87V21071-01 ML87V21071 Copyright 2005 Oki Electric Industry Co., Ltd. 123/123 ...