ml87v21071 Oki Semiconductor, ml87v21071 Datasheet - Page 11

• Manufacturer Part Number: ml87v21071
• Description: Video Signal Noise Reduction Ic With A Built-in Frame Memory
• Manufacturer: Oki Semiconductor

FUNCTIONAL DESCRIPTION
1. Input/Output
1.1 Memory Control
1.1.1 Input Control Mode Settings
OKI Semiconductor
[1]
The ML87V21071 accesses data to the input data frame memory by generating a line access type memory control
signal from Sync. signals of the IVS and IHS pin inputs or the Sync. signals separated from SAV and EAV, and
achieves noise reduction of frame/field/line adaptation recursive type.
As shown in the table below, this IC offers a choice of 12 input control modes including the progressive mode by
the INPR setting (SUB:44h-bit[7]), which can be selected by setting either the external setting pin mode (IRMON
= 0 (SUB: 40h–bit [7]) or internal register mode (IRMON = 1).
In ITU-R BT.656 input mode and in the mode of valid 720 pixels in the horizontal direction (HMD[1:0]=0h), the
IC checks the mode by measuring the blanking period (between EAV and SAV) of the timing reference code of
the input data (YI[7:0]) and automatically sets VMD[0] by setting APN656 = 1 (SUB: 41h-bit[2]).
During APN656=1, do not set any value other than HMD[1:0]=1.
The input system internal clock frequency f
0
0
0
0
0
0
VMD
Other than above
16-bit input mode: f
8-bit input mode/ITU-R BT.656 mode: f
[0]
0
1
0
1
0
1
[1]
0
0
0
0
1
1
HMD
IRMON
Table F1-1-1 (3) Input Control Mode Settings(INPR=0: Interlace)
0
1
[0]
0
0
1
1
0
0
Table F1-1-1 (1) Input Control Mode Setting Allocation 1
Table F1-1-1 (2) Input Control Mode Setting Allocation 2
Vertical mode
IICLK
625/50Hz 2:1
525/60Hz 2:1
625/50Hz 2:1
525/60Hz 2:1
625/50Hz 2:1
525/60Hz 2:1
SUB:40h-bit[1]
SUB:40h-bit[1]
* In progressive mode, neither 8-bit input mode nor ITU-R BT.656 input mode can be
= f
seected.
[1]
INPR
ICLK
0
1
VMD
Number of
valid lines
IICLK
SUB:40h-bit[0]
Progressive (525p/625p)
(External pin)
IICLK
288
243
288
243
288
243
Interlace (525i/625i)
MODE 0
is as follows:
= f
[0]
ICLK
Mode
/2
Standard clock
frequency f
12.272727/
14.75/29.5
24.545454
14.75/29.5
Test modes
14.31818/
28.63636
13.5/27
13.5/27
SUB:40h-bit[3]
SUB:40h-bit[3]
[MHz]
[1]
ICLK
HMD
Standard pixels
SUB:40h-bit[2]
per line
(External pin)
864
858
944
780
944
910
MODE 1
[0]
PEDL87V21071-01
Valid pixels
ML87V21071
720
720
768
640
768
768
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