msx532 Fairchild Semiconductor, msx532 Datasheet - Page 14

• Manufacturer Part Number: msx532
• Description: 532 Port Digital Crosspoint Switch With Lvttl I/o S
• Manufacturer: Fairchild Semiconductor

www.fairchildsemi.com
Introduction
JTAG Interface
The dedicated JTAG TAP interface is designed in compli-
ance with the IEEE-1149.1. The standard interface has five
pins: Test Data Out (TDO), Test Mode Select (TMS), Test
Data In (TDI), Test Reset (TRST), and Test Clock (TCK)
which allow Boundary Scan Testing as well as device con-
figuration and verification. Data on the TDI and TMS pins
are clocked into the device on the rising edge of the TCK
signal, while the valid data appears on the TDO pin after
the falling edge of TCK. For more detailed information on
JTAG programming, refer to the MSX Family Register Pro-
gramming Manual.
Note 1: If both IE_1 and IE_2 are selected, the two are assigned an OR function to form the IE. Either can be “1” to enable the input.
Note 2: If both OE_1 and OE_2 are selected, active LOW signals are assigned an AND function to form the resulting OE. Either can be “0” to enable the out-
put.
RCB[0]
Signal
Bit Number
10
12
13
14
15
16
17
18
19
11
0
1
2
3
4
5
6
7
8
9
Inverted Output Clock. When this bit is set to a one, the registered output port’s selected clock source will be
inverted. When zero the output clock source will not be inverted.
Input (IN)
Output (OP)
Bus Repeater (BR)
Reg In Clock 1
Reg In Clock 2
Reg In Clock Neighbor
Reg Out Clock 1
Reg Out Clock 1
Reg Out Clock Neighbor Selects Reg. Out I/O Buffer, Neighbor
Input Enable 1 (IE_1)
Input Enable 2 (IE_2)
Output Enable 1 (OE_1) Select Output Enable 1 (Note 2)
Output Enable 2 (OE_2) Select Output Enable 2 (Note 2)
Force 1
Force 0
Array 1
Array 0
Invert Output
Invert Input Clock
Invert Output Clock
I/O Buffer Function
(Continued)
TABLE 7. I/O Buffer Programming Bit Functions
Input Pin Data to Drive Array
Output Array Data to Pin
Low Array Signal, Drive Pin LOW
Low Pin Signal, Drive Array LOW
Selects Reg. In I/O Buffer, Clock 1
Selects Reg. In I/O Buffer, Clock 2
Selects Reg. In I/O Buffer, Neighbor
Selects Reg. Out I/O Buffer, Clock 1
Selects Reg. Out I/O Buffer, Clock 2
Select Input Enable 1 (Note 1)
Select Input Enable 2 (Note 1)
Force I/O Buffer Output Pin to a 1
Force I/O Buffer Output Pin to a 0
Force I/O Buffer Array to a 1
Force I/O Buffer Array to a 0
Output data is inverted.
This operation is invalid in Bus Repeater mode and Register Output mode
Invert the Clock to the Input Register
Invert the Clock to the Output Register
14
Description
I/O Buffer Programming
The JTAG I/O Buffer Data Register where data is held, is
used to program the I/O buffer. This register is used with
the JTAG interface only. The JTAG I/O buffer data register
is 20 bits wide. Power on reset, RapidConfigure reset,
Hardware reset, and JTAG reset programs all Ports as
inputs. JTAG can be reset via the TRST pin or by clocking
five consecutive ones to the TMS pin. The HW_RST (hard-
ware reset) pin resets and breaks all connections in the
Crosspoint Array to all no-connects, and the I/O buffers to
inputs.
Table 7 lists the bits and their function in JTAG mode.
These are internal bits as shifted into the I/O buffer data
register for I/O buffer programming.
Description