ht82a851r Holtek Semiconductor Inc., ht82a851r Datasheet - Page 24

• Manufacturer Part Number: ht82a851r
• Description: Ht82a851r -- Usb Audio Mcu
• Manufacturer: Holtek Semiconductor Inc.

Rev. 1.20
SBDR: Serial bus data register
Data written to SBDR
Data read from SBDR
Clock polarity = rising (CLK) or falling (CLK): 1 or 0 (software option)
Serial Interface Operation:
WCOL: master/slave mode, set if writing to SBDR when data is transferring (transmitting or receiving) and this writing
will be ignored. The WCOL function can be enabled/disabled by a software option (SIO_WCOL bit of MODE_CTRL
register). WCOL is set by SIO and cleared by the user.
Data transmission and reception will continue to operated when the MCU enters the power-down mode.
CPOL is used to select the clock polarity of CLK and is a software option (SIO_CPOL bit of MODE_CTRL register).
MLS: MSB or LSB first selection
CSEN: chip select function enable/disable, CSEN = 1
SCS signal before the CLK signal and slave data transferring should be disabled(enabled) before(after) SCS signal
received. CSEN = 0, SCS signal is not needed, SCS pin (master and slave) should be floating.
CSEN: CSEN software option (SIO_CSEN bit of MODE_CTRL register) is used to enable/disable software CSEN
function. If CSEN software option is disable, software CSEN always disabled. If CSEN software option is enabled,
software CSEN function can be used.
SBEN = 1
CLK = output 1/0 (dependent on CPOL software option), slave CLK = floating
SBEN = 0
TRF is set by SIO and cleared by the user. When the data is transferring (transmission and reception) is complete,
TRF is set to generate SBI (serial bus interrupt).
Operating Mode description:
Master transmitter: clock sending and data I/O started by writing to SBDR
Master clock sending started by writing to SBDR
Slave transmitter: data I/O started by clock reception
Slave receiver: data I/O started by clock reception
Slavehans
Master
Label
serial bus standby; SCS (CSEN = 1) = 1; SCS = floating (CSEN = 0); SDI = floating; SDO = 1; master
serial bus disable; SCS = SDI = SDO = CLK = floating
Select CKS and select M1,M0 = 00, 01, 10
Select CSEN, MLS (same as slave)
Set SBEN
Writing data to SBDR
to step 5
into the TXRX buffer
Check WCOL; WCOL = 1
Check TRF or waiting for SBI (serial bus interrupt)
Read data from SBDR
Clear TRF
Go to step 4
CKS don t care and select M1, M0 = 11
Select CSEN, MLS (same as master)
Set SBEN
Writing data to SBDR
SCS): CLK
TXRX buffer and SDI data is shifted into the TXRX buffer
buffer is latched into SBDR)
Check WCOL; WCOL = 1
Check TRF or waiting for SBI (serial bus interrupt)
Read data from SBDR
Clear TRF
Go to step 4
write data to the TXRX buffer only
read from SBDR only
(SIO internal operation
go to step 5
data transferred, data in the TXRX buffer is latched into SBDR)
data is stored in the TXRX buffer
data is store in the TXRX buffer
clear WCOL and go to step 4; WCOL = 0
clear WCOL, go to step 4; WCOL = 0
(SIO internal operations
24
data stored in the TXRX buffer, and the SDI data is shifted
SCS signal function is active. The master should output a
Functions
CLK (SCS) received
output CLK (and SCS) signals
waiting for master clock signal (and
data transferred, data in the TXRX
go to step 6
go to step 6
HT82A851R
June 15, 2007
output data in
go