ht82a851r Holtek Semiconductor Inc., ht82a851r Datasheet - Page 20

• Manufacturer Part Number: ht82a851r
• Description: Ht82a851r -- Usb Audio Mcu
• Manufacturer: Holtek Semiconductor Inc.

The MISC register combines command and status to control the desired endpoint FIFO action and to show the status of
the desired endpoint FIFO. MISC will be cleared by a USB reset signal.
Note: *USB definition: when the host sends a set Configuration , the Data pipe should send the DATA0 (about the
The speaker output volume and speaker mute/un-mute are controlled by the USB Speaker Volume Control register.
The range of the volume is set from 6 dB to -32 dB by software.
Speaker mute control:
MUTE=0: Mute Speaker output
MUTE=1: Normal
Rev. 1.20
Bit No.
Bit No.
Bit No.
5~7
0~6
0
1
2
3
4
5
6
7
0
1
2
3
4
7
Data toggle) first. So, when the Device receives a set configuration setup command, the user needs to toggle
this bit as the following data will send a Data0 first.
**It is only required to set the data pipe as an input pile or output pile. The purpose of this function is to avoid the
host sending a abnormal IN or OUT token and disabling the endpoint.
ISO_OUT_EN
ISO_IN_EN
REQUEST
DATATG*
SETCMD
SETIO1**
SETIO2**
SETIO3**
SETIO4**
USVC0~
USVC6
READY
CLEAR
MUTE
Label
Label
Label
LEN0
SETIO (27H) Register, USB Endpoint 1 ~ Endpoint 4 Set IN/OUT Pipe Register
TX
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
USB Speaker Volume Control (1CH) Register
Power-on
Power-on
Power-on
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
MISC (26H) Register
After setting the status of the desired one, FIFO can be requested
by setting this bit high . After finishing, this bit must be set low.
To represent the direction and transition end MCU access. When
set to logic 1, the MCU desires to write data to the FIFO. After
finishing, this bit must be set to logic 0 before terminating request to
represent transition end. For an MCU read operation, this bit must
be set to logic 0 and set to logic 1 after finishing.
MCU requests to clear the FIFO, even if the FIFO is not ready. After
clearing the FIFO, the USB interface will send force_tx_err to tell
the Host that data under-run if the Host wants to read data.
Enables the isochronous in pipe interrupt.
Enables the isochronous out pipe interrupt.
To show that the data in the FIFO is a setup command. This bit will
remain in this state until the next one enters the FIFO.
To show that the desired FIFO is ready
To show that the host sent a 0-sized packet to the MCU. This bit
must be cleared by a read action to the corresponding FIFO.
DATA token toggle bit
Set endpoint1 input or output pipe (1/0), default input pipe(1)
Set endpoint2 input or output pipe (1/0), default output pipe(0)
Set endpoint3 input or output pipe (1/0), default input pipe(1)
Set endpoint4 input or output pipe (1/0), default input pipe(1)
Undefined bit, read as 0
Volume control Bit0~Bit6
Mute control, low active.
20
Functions
Functions
Functions
HT82A851R
June 15, 2007