ht82a851r Holtek Semiconductor Inc., ht82a851r Datasheet
ht82a851r
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ht82a851r Summary of contents
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... Low voltage reset function (3.0V 0.3V) 24-pin SSOP package gle chip. The play frequency in the HT82A851R oper- ates at a sampling rate of 48/8kHz. HT82A851R has a digital programmable gain amplifier. The gain range is from 32dB to +6dB. For the Isochronous input, the digi- tal gain range is from 0dB to 19.5dB. ...
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... Block Diagram Pin Assignment Rev. 1.20 2 HT82A851R June 15, 2007 ...
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... Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.20 Description +6.0V Storage Temperature ............................ 125 C SS +0.3V Operating Temperature........................... Total............................................................ 100mA OH 3 HT82A851R June 15, 2007 ...
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... No load, system HALT, 5V USB transceiver and 3.3V regulator 0. 0. =0. =0. 2 5mA 3.0 V33O Test Conditions Min. V Conditions HT82A851R Ta=25 C Typ. Max. Unit 5.0 5 350 3.0 3.3 V 3.3 3.6 V Ta=25 C Typ ...
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... Program Counter S10 Program Counter S11~S0: Stack register bits @7~@0: PCL bits 5 HT82A851R * ...
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... TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Table Location * Table Location P11~P8: Current program counter bits when TBHP is disabled @7~@0: Table pointer bits 6 HT82A851R * June 15, 2007 ...
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... Except for some dedicated bits, each bit in the data memory can be set and reset by SET [m].i and CLR [m].i . They are also indirectly accessible through the memory pointer registers, MP0 or MP1. Rev. 1.20 RAM Mapping 7 HT82A851R June 15, 2007 ...
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... Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other Function Status (0AH) Register 8 HT82A851R June 15, 2007 ...
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... When the HT82A851R receives a USB Suspend signal from the Host PC, the suspend line (bit0 of USC) of the HT82A851R is set and a USB interrupt is also triggered. Also when the HT82A851R receives a Resume signal from the Host PC, the resume line (bit3 of USC) of the HT82A851R is set and a USB interrupt is triggered ...
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... The serial interface interrupt is indicated by the interrupt flag (SIF; bit 5 of INTC1), that is generated by the reception or transfer of a complete 8-bits of data between the HT82A851R and the external device. The serial interface interrupt is controlled by setting the Serial interface interrupt control bit (ESII; bit 1 of INTC1). After the interrupt is enabled (by setting SBEN ...
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... If an interrupt request flag is set to 1 before entering the Power-down mode, the wake-up function of the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 t periods) to resume normal operation, i.e., a dummy period is inserted. If the wake-up results from an 11 HT82A851R (system clock SYS June 15, 2007 ...
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... The functional unit chip reset status are shown below. Program Counter 000H Interrupt Disable Clear. After master reset, WDT WDT begins counting Timer/event Counter Off Input/output Ports Input mode Stack Pointer Points to the top of the stack Reset Circuit Reset Timing Chart Reset Configuration 12 HT82A851R June 15, 2007 ...
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... HT82A851R USB Reset USB Reset (Normal) (HALT) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu ...
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... TON bit can only be reset by instructions. A Timer/Event Counter overflow is one of the wake-up sources. No matter what the operational mode is, writing ET0I or ET1I disables the related interrupt service. 14 HT82A851R USB Reset USB Reset (Normal) (HALT) 0uuu 0000 ...
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... For example, SET [m].i , CLR [m].i , CPL [m] , CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. 15 HT82A851R June 15, 2007 ...
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... Also the user can further decrease the suspend current by setting SUSP2 (bit4 of the UCC). When the resume signal is sent out by the host, the HT82A851R will be woken up by the USB interrupt and Rev. 1.20 Input/Output Ports the Resume line (bit 3 of USC) will be set. In order to ...
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... USB Interface The HT82A851R device has 5 Endpoints (EP0~EP4). EP0 supports Control transfer. EP1 and EP4 support Interrupt transfer. EP2 supports Isochronous out transfer. EP3 supports Isochronous in transfer. These registers, including USC (20H), USR (21H), UCC (22H), AWR (23H), STALL (24H), SIES (25H), MISC (26H), FIFO0 (28H), FIFO1 (29H), FIFO2 (2AH), FIFO3 (2BH), FIFO4 (2CH) are used for the USB function ...
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... PLL output - 16MHz Used to specify the system clock oscillator frequency used by MCU 6MHz crystal oscillator or resonator is used, this bit should be set 12MHz crystal oscillator or resonator is used. this bit should be cleared UCC (22H) Register 18 HT82A851R June 15, 2007 ...
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... NAK token interrupt mask flag. If this bit set, when the device sent a NAK token to the host, an interrupt will be disabled. Otherwise if this bit is cleared, when the device sends a NAK token to the host, it will enter the interrupt sub-routine. SIES (25H) Register 19 HT82A851R June 15, 2007 ...
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... Set endpoint1 input or output pipe (1/0), default input pipe(1) 0 Set endpoint2 input or output pipe (1/0), default output pipe(0) 1 Set endpoint3 input or output pipe (1/0), default input pipe(1) 1 Set endpoint4 input or output pipe (1/0), default input pipe(1) Undefined bit, read as 0 Functions 0 Volume control Bit0~Bit6 0 Mute control, low active. 20 HT82A851R June 15, 2007 ...
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... Speaker Volume Control Table Functions Functions PGA_CTRL (30H) Register 0 0 19.5 19 19.5 21 HT82A851R Result (dB) USVC 24 101_1100 101_1011 25 101_1010 26 27 101_1001 101_1000 28 101_0111 29 30 101_0110 101_0101 31 101_0100 32 Gain (dB) June 15, 2007 ...
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... PFDD PFDD7 PFDD6 The PFD (programmable frequency divider) is implemented in the HT82A851R composed of two portions: a prescaler and a general counter. The prescaler is controlled by the register bits, PRES0 and PRES1. The 4-stage prescaler is divided by 16. The general counter is programmed by an 8-bit register PFDD. ...
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... SBEN MLS /2, select select as 1 SIO SYS SIO SYS /4 /16 start transmission/reception automatically set TRF Functions used to generate an interrupt 23 HT82A851R CSEN WCOL TRF June 15, 2007 ...
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... TXRX buffer waiting for master clock signal (and (SIO internal operations CLK (SCS) received data transferred, data in the TXRX clear WCOL step 4; WCOL = 0 SCS signal function is active. The master should output a 24 HT82A851R step 6 output data step 6 June 15, 2007 ...
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... SBCR CKS Serial Bus Control Register Default 0 SBDR D7 Serial Bus Data Register Default U Rev. 1.20 SIO Timing SBEN MLS Block Diagram of SIO 25 HT82A851R CSEN WCOL TRF June 15, 2007 ...
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... Functions MODE_CTRL (34H) Register ;12MHz SYSCLK ;SPI Chip Select Function Enable ;falling edge change data ;fSIO=f /2 SYS ;clear TRF flag ;clear Interrupt SPI flag ;MSB shift first ;Chip Select Enable ;SPI Enable, SCS will go low ;SPI Interrupt Disable 26 HT82A851R June 15, 2007 ...
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... Bit 5 Bit 4 Bit 3 PL_D6 PL_D5 PL_D4 PL_D3 PR_D6 PR_D5 PR_D4 PR_D3 R_D6 R_D5 R_D4 R_D3 R_D14 R_D13 R_D12 R_D11 Option 27 HT82A851R Bit 2 Bit 1 Bit 0 PL_D2 PL_D1 PL_D0 PL_D9 PL_D8 PR_D2 PR_D1 PR_D0 PR_D8 R_D2 R_D1 R_D0 R_D10 R_D9 R_D8 June 15, 2007 ...
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... Application Circuits Rev. 1.20 28 HT82A851R June 15, 2007 ...
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... These instructions are the key to decision making and branching within the pro- gram perhaps determined by the condition of certain in- put switches or by the condition of internal data bits. 29 HT82A851R June 15, 2007 ...
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... Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Description 30 HT82A851R Cycles Flag Affected AC, OV Note AC AC ...
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... For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.20 Description 31 HT82A851R Cycles Flag Affected 1 None Note 1 ...
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... Operation ACC ACC AND x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. Operation [m] ACC AND [m] Affected flag(s) Z Rev. 1.20 32 HT82A851R June 15, 2007 ...
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... The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO 0 PDF 0 Affected flag(s) TO, PDF Rev. 1.20 addr 33 HT82A851R June 15, 2007 ...
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... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO 0 PDF 1 Affected flag(s) TO, PDF Rev. 1. HT82A851R June 15, 2007 ...
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... No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. Operation ACC ACC OR [m] Affected flag(s) Z Rev. 1.20 addr 35 HT82A851R June 15, 2007 ...
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... The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) None Rev. 1.20 Stack Stack Stack [m]. 0~6) 36 HT82A851R June 15, 2007 ...
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... Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i [m].(i+1 0~6) ACC [m].0 Affected flag(s) C Rev. 1.20 [m]. 0~6) 37 HT82A851R June 15, 2007 ...
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... Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i 1 Affected flag(s) None Rev. 1.20 [ HT82A851R June 15, 2007 ...
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... The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ACC Affected flag(s) OV, Z, AC, C Rev. 1.20 0 [m] [ HT82A851R June 15, 2007 ...
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... The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] program code (low byte) TBLH program code (high byte) Affected flag(s) None Rev. 1.20 [m].7 ~ [m].4 [m].7 ~ [m].4 [m].3 ~ [m].0 40 HT82A851R June 15, 2007 ...
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... The result is stored in the Data Memory. Operation [m] ACC XOR [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ACC XOR x Affected flag(s) Z Rev. 1.20 41 HT82A851R June 15, 2007 ...
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... Package Information 24-pin SSOP (209mil) Outline Dimensions Symbol Rev. 1.20 Dimensions in mil Min. Nom. 291 196 9 311 HT82A851R Max. 323 220 15 345 June 15, 2007 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.20 43 HT82A851R June 15, 2007 ...