ht82a851r Holtek Semiconductor Inc., ht82a851r Datasheet - Page 10

• Manufacturer Part Number: ht82a851r
• Description: Ht82a851r -- Usb Audio Mcu
• Manufacturer: Holtek Semiconductor Inc.

The internal Timer/Event counter 1 interrupt is initialized
by setting the Timer/Event Counter 1 interrupt request
flag (bit 6 of INTC0), caused by a timer 1 overflow. When
the interrupt is enabled, the stack is not full and T1F is
set, a subroutine call to location 0CH will occur. The
related interrupt request flag (T1F) will be reset and the
EMI bit cleared to disable further interrupts.
The play interrupt is initialized by setting the play
interrupt request flag (bit 4 of INTC1), caused by a play
data valid. When the interrupt is enabled, the stack is not
full and the PLAYF is set, a subroutine call to location
10H will occur. The related interrupt request flag
(PLAYF) will be reset and the EMI bit cleared to disable
further interrupts. If PLAY_MODE (bit 3 of MODE_CTRL
register) is set to 1 , the play interrupt frequency will
change to 8kHz, otherwise the interrupt frequency is
48kHz.
The serial interface interrupt is indicated by the interrupt
flag (SIF; bit 5 of INTC1), that is generated by the
reception or transfer of a complete 8-bits of data
between the HT82A851R and the external device. The
serial interface interrupt is controlled by setting the
Serial interface interrupt control bit (ESII; bit 1 of
INTC1). After the interrupt is enabled (by setting SBEN;
bit 4 of SBCR), and the stack is not full and the SIF is set,
a subroutine call to location 14H occurs.
The record interrupt is initialized by setting the record
interrupt request flag (bit 6 of INTC1), caused by a
record frequency time out (8kHz). When the interrupt is
enabled, the stack is not full and RECF is set, a
subroutine call to location 18H will occur. The related
interrupt request flag (RECF) will be reset and the EMI
bit cleared to disable further interrupts.
During the execution of an interrupt subroutine, other
interrupt acknowledge signals are held until the RETI
instruction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, RET or RETI
may be invoked. RETI will set the EMI bit to enable an
interrupt service, but RET will not.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding
interrupts are enabled. In the case of simultaneous
requests the following table shows the priority that is
applied. These can be masked by resetting the EMI bit.
Rev. 1.20
USB interrupt
Timer/Event Counter 0 overflow
Timer/Event Counter 1 overflow
Play Interrupt
Serial Interface Interrupt
Record Interrupt
Interrupt Source
Priority
1
2
3
4
5
6
Vector
0CH
04H
08H
10H
14H
18H
10
It is recommended that a program does not use the
Interrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications. If
only one stack is left and enabling the interrupt is not
well controlled, the original control sequence will be
damaged once the CALL operates in the interrupt
subroutine.
Oscillator Configuration
The microcontroller contains an integrated oscillator cir-
cuit.
This oscillator is designed for the system clock. The
HALT mode stops the system oscillator and ignores any
external signals to conserve power.
A crystal across OSCI and OSCO is needed to provide
the feedback and phase shift required for the oscillator.
No other external components are required. If preferred,
a resonator can also be connected between OSCI and
OSCO for oscillation to occur, but two external
capacitors connected between OSCI, OSCO and
ground are required.
The WDT oscillator is a free running on-chip RC oscilla-
tor, and no external components are required. Even if
the system enters the power down mode, the system
clock stops running, but the WDT oscillator still
continues to run. The WDT oscillator can be disabled by
a configuration option to conserve power.
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or the instruction clock
(system clock/4). The timer is designed to prevent a
software malfunction or sequence from jumping to an
unknown location with unpredictable results. The WDT
can be disabled by a configuration option. However, if
the WDT is disabled, all executions related to the WDT
lead to no operation.
When the WDT clock source is selected, it will be first
divided by 256 (8-stage) to get the nominal time-out
period. By invoking the WDT prescaler, longer time-out
periods can be realized. Writing data to WS2, WS1,
WS0 can give different time-out periods.
The WDT OSC period is typically 65 s. This time-out
period may vary with temperature, VDD and process
variations. The WDT OSC always keeps running in any
operation mode.
CALL subroutine within the interrupt subroutine.
System Oscillator
HT82A851R
June 15, 2007