ht82a851r Holtek Semiconductor Inc., ht82a851r Datasheet - Page 11

• Manufacturer Part Number: ht82a851r
• Description: Ht82a851r -- Usb Audio Mcu
• Manufacturer: Holtek Semiconductor Inc.

If the instruction clock is selected as the WDT clock
source, the WDT operates in the same manner except in
the halt mode. In the HALT mode, the WDT stops count-
ing and lose its protecting purpose. In this situation the
logic can only be re-started by external logic. The high
nibble of the WDTS is reserved for the DAC write mode.
The WDT overflow under normal operation initializes a
mode, the overflow initializes a warm reset , and only
the program counter and stack pointer are reset to zero.
To clear the contents of the WDT, there are three meth-
ods to be adopted, i.e., an external reset (a low level to
RESET), a software instruction, and a HALT instruc-
tion. There are two types of software instructions; CLR
WDT and the other set CLR WDT1 and CLR
WDT2 . Of these two types of instruction, only one type
of instruction can be active at a time depending on the
configuration option CLR WDT times selection option.
If the CLR WDT is selected (i.e., CLR WDT times
equal one), any execution of the CLR WDT instruction
clears the WDT. In the case that CLR WDT1 and CLR
WDT2 are chosen (i.e., CLR WDT times equal two),
these two instructions have to be executed to clear the
WDT; otherwise, the WDT may reset the chip due to a
time-out.
Power Down Operation - HALT
The Power-down mode is entered by the execution of a
Rev. 1.20
chip reset and sets the status bit TO . In the HALT
HALT instruction and results in the following:
The system oscillator will be turned off but the WDT
oscillator keeps running if the internal WDT oscillator
is selected.
The contents of the on-chip data memory and regis-
ters remain unchanged.
Bit No.
3~7
0
1
2
Label
WS0
WS1
WS2
Watchdog Timer division ratio selection bits
Bit 2,1,0 = 000, Division Ratio = 1:1
Bit 2,1,0 = 001, Division Ratio = 1:2
Bit 2,1,0 = 010, Division Ratio = 1:4
Bit 2,1,0 = 011, Division Ratio = 1:8
Bit 2,1,0 = 100, Division Ratio = 1:16
Bit 2,1,0 = 101, Division Ratio = 1:32
Bit 2,1,0 = 110, Division Ratio = 1:64
Bit 2,1,0 = 111, Division Ratio = 1:128
Unused bit, read as 0
WDTS (09H) Register
Watchdog Timer
11
The system can leave the Power-down mode by means
of an external reset, an interrupt, an external falling
edge signal on port A or a WDT overflow. An external
reset causes a device initialisation and the WDT
overflow performs a warm reset . After the TO and PDF
flags are examined, the cause for the device reset can
be determined. The PDF flag is cleared by a system
power-up or by executing the CLR WDT instruction
and is set when executing the HALT instruction. The
TO flag is set if the WDT time-out occurs, and causes a
wake-up that only resets the program counter and SP;
the others remain in their original status.
A port A wake-up and interrupt methods can be
considered as a continuation of normal execution. Each
pin in port A can be independently selected to wake-up
the device using configuration options. After awakening
from an I/O port stimulus, the program will resume
execution at the next instruction. If the device is
awakened from an interrupt, two sequence may occur. If
the related interrupt is disabled or the interrupt is
enabled but the stack is full, the program will resume
execution at the next instruction. If the interrupt is
enabled and the stack is not full, the regular interrupt
response takes place. If an interrupt request flag is set to
function of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 t
periods) to resume normal operation, i.e., a dummy
period is inserted. If the wake-up results from an
1 before entering the Power-down mode, the wake-up
The WDT and WDT prescaler will be cleared and will
start counting again if the WDT clock is sourced from
the internal WDT oscillator.
All of the I/O ports remain in their original condition.
The PDF flag is set and the TO flag is cleared.
Function
HT82A851R
SYS
June 15, 2007
(system clock