spear-09-p022 STMicroelectronics, spear-09-p022 Datasheet - Page 8

• Manufacturer Part Number: spear-09-p022
• Description: Spear?? Plus600 Dual Processor Cores
• Manufacturer: STMicroelectronics

Product Overview
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Architecture properties
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ADC (1us/1MSPS) 8 analog input channel; 10bit approximation.
JPEG codec accelerator 1clock/pixel.
10 independent Timers with programmable prescaler.
RTC - WDOG - SYSCTR - MISC internal control registers.
JTAG (IEEE1149.1) interface.
Dual symmetric processor architecture:
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Power save features:
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Customizable logic to embed the customer real 'core competence':
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Architecture easily extensible.
External memory bandwidth of each master tuneable to meet the target performances
of different applications.
All internal peripherals are shared, allowing flexible and efficient SW partitions.
High throughput can be sustained in aggregate way splitting critical tasks either
onto additional CPUs and optional HW accelerators engines.
Critical resources are private to each CPU (interrupt controller and OS Timers).
Both processors are equipped with ICE and ETM configurable debug interfaces.
Operating frequency SW programmable.
Clock gating functionality.
Low frequency operating mode.
Automatic power saving controlled from application activity demands.
600Kgate standard cell array.
Internal memory pool (128Kbyte) full configurable.
Up to 16 external/internal source clock (some of these programmable).
Three memory path toward the SDRAM controller to ensure a good bandwidth.
SPEAR-09-P022